View DSP56300FM_8371202.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? freescale semiconductor, inc., 2006. all rights reserved. freescale semiconductor technical data this document contains information on a new product. specificatio ns and information herein are su bject to change without notice . document number: dsp56362 rev. 4, 08/2006 1 overview freescale semiconductor, in c. designed the dsp56362 to support digital audio appl ications requiring digital audio compression and decompression, sound field processing, acoustic equalizati on, and other digital audio algorithms. the dsp56362 uses the high performance, single-clock-per-cycle ds p56300 core family of programmable cmos digital signal processors (dsps) combined with the audio signa l processing capability of the freescale symphony? dsp family, as shown in figure 1-1 . this design provides a two-fold performance increase over freescale?s popular symphony family of dsps while retaining code compatibility. significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (dma). the dsp56362 offers 100 million instructions per second (mi ps) using an internal 100 mhz clock at 3.3 v. dsp56362 24-bit audio digital signal processor contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 signal/connection descriptions . . . . . . . . . 2-1 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5 design considerations . . . . . . . . . . . . . . . . 5-1 6 ordering information . . . . . . . . . . . . . . . . . . 6-1 a power consumption benchmark . . . . . . . . a-1 b ibis model . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1
overview dsp56362 technical data, rev. 4 1-2 freescale semiconductor figure 1-1 dsp56362 block diagram data sheet conventions this data sheet uses the following conventions: overbar used to indicate a si gnal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage* pin true asserted v il / v ol pin false deasserted v ih / v oh pin true asserted v ih / v oh pin false deasserted v il / v ol note: *values for v il , v ol , v ih , and v oh are defined by individual product specifications. pll once? clock generator internal data bus switch yab xab pab ydb xdb pdb gdb modb/irqb modc/irqc external data bus switch 11 modd/irqd dsp56300 12 16 24-bit 24 18 ddb dab peripheral core ym_eb xm_eb pm_eb pio_eb expansion area shi jtag 6 5 reset moda/irqa pinit/nmi extal address control data triple timer host interface esai address generation unit six channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators 56-bit barrel shifter power mngmnt. dram/sram bus interface & i - cache control external address bus switch aa0456g memory expansion area program ram/ instruction cache 3072 24 program rom 30k 24 bootstrap rom 192 24 x data ram 5632 24 rom 6144 24 y data ram 5632 24 rom 6144 24 clkout dax (spdif) 2
overview dsp56362 technical data, rev. 4 freescale semiconductor 1-3 1.1 features ? multimode, multichannel dec oder software functionality ? dolby digital and pro logic ? mpeg2 5.1 ?dts ? bass management ? digital audio post-processing capabilities ? 3d virtual surround sound ? lucasfilm thx5.1 ? soundfield processing ? equalization ? digital signal processing core ? 100 mips with a 100 mhz clock at 3.3 v +/- 5% ? object code compatible with the dsp56000 core ? highly parallel instruction set ? data arithmetic logic unit (alu) ? fully pipelined 24 x 24-bit parall el multiplier-accumulator (mac) ? 56-bit parallel barrel shifter (fast shift and normalization; bit stream gene ration and parsing) ? conditional alu instructions ? 24-bit or 16-bit arithmetic support under software control ? program control unit (pcu) ? position independent code (pic) support ? addressing modes optimized for dsp appl ications (including immediate offsets) ? on-chip instruction cache controller ? on-chip memory-expandable hardware stack ? nested hardware do loops ? fast auto-return interrupts ? direct memory access (dma) ? six dma channels supporting internal and external accesses ? one-, two-, and three- dimensional tr ansfers (including ci rcular buffering) ? end-of-block-transfer interrupts ? triggering from interrupt lines and all peripherals ? phase-locked loop (pll) ? software programmable pll-based freque ncy synthesizer for the core clock ? allows change of low-power divide factor (df) without loss of lock ? output clock with skew elimination ? hardware debugging support
overview dsp56362 technical data, rev. 4 1-4 freescale semiconductor ? on-chip emulatio n (once?) module ? joint action test group (jta g) test access port (tap) ? address trace mode reflects internal pr ogram ram accesses at the external port ? on-chip memories ? modified harvard architecture allows simult aneous access to program and data memories ? 30720 x 24-bit on-chip program rom 1 (disabled in 16-bit compatibility mode) ? 6144 x 24-bit on-chip x-data rom 1 ? 6144 x 24-bit on-chip y-data rom 1 ? program ram, instruction cache, x data ram, and y data ram sizes are programmable . ? 192 x 24-bit bootstrap rom (disabled in sixteen-bit compatibility mode) ? off-chip memory expansion ? data memory expansion to 256k x 24-bit word memory for p, x, and y memory using sram. ? data memory expansion to 16m x 24-bit word memory for p, x, and y memory using dram. ? external memory expansion port( twenty-four da ta pins for high speed external memory access allowing for a large number of external accesses per sample) ? chip select logic for glueless interface to srams ? on-chip dram controller fo r glueless interface to drams ? peripheral and support circuits ? enhanced serial audio interface (esai) includes: ? six serial data lines, 4 se lectable as receive or tr ansmit and 2 transmit only. ? master or slave capability ?i 2 s, sony, ac97, and other audi o protocol implementations ? serial host interface (shi) features: ? spi protocol with mu lti-master capability ?i 2 c protocol with single-master capability ? ten-word receive fifo ? support for 8-, 16-, and 24-bit words. ? byte-wide parallel host inte rface (hdi08) with dma support ? dax features one serial tr ansmitter capable of supporting s/pdif, ie c958, iec1937, cp-340, and aes/ebu digital audio formats; alternate configuration supports up to two gpio lines 1. these roms may be factory programmed with data or programs provided by the application developer. instruction cache switch mode program ram size instruction cache size x data ram size y data ram size disabled disabled 3072 24-bit 0 5632 24-bit 5632 24-bit enabled disabled 2048 24-bit 1024 24-bit 5632 24-bit 5632 24-bit disabled enabled 5120 24-bit 0 5632 24-bit 3584 24-bit enabled enabled 4096 24-bit 1024 24-bit 5632 24-bit 3584 24-bit
overview dsp56362 technical data, rev. 4 freescale semiconductor 1-5 ? triple timer module with single ex ternal interface or gpio line ? on-chip peripheral registers are me mory mapped in data memory space ? reduced power dissipation ? very low-power (3.3 v) cmos design ? wait and stop low-power standby modes ? fully-static logic, operation frequency down to 0 hz (dc) ? optimized power management circuitry (ins truction-dependent, peri pheral-dependent, and mode-dependent) 1.2 package ? 144-pin plastic thin quad flat pa ck (lqfp) surface-mount package 1.3 documentation table 1-1 lists the documents that provide a complete description of the dsp 56362 and are required to design properly with the part. docume ntation is available from a local freescale distributor, a freescale semiconductor sales office, a freescal e literature distributi on center, or through the freescale dsp home page on the internet (the sour ce for the latest information). table 1-1 dsp56362 documentation document name description order number dsp56300 family manual detailed descript ion of the 56000-family architecture and the 24-bit core processor and instruction set DSP56300FM dsp56362 user?s manual detailed description of memory, peripherals, and interfaces dsp56362um dsp56362 product brief brief description of the chip dsp56362p dsp56362 data sheet (this document) electrical and timing specifications; pin and package descriptions dsp56362
overview dsp56362 technical data, rev. 4 1-6 freescale semiconductor notes
dsp56362 technical data, rev. 4 freescale semiconductor 2-1 2 signal/connection descriptions 2.1 signal groupings the input and output signals of th e dsp56362 are organized into functi onal groups, which are listed in table 2-1 and illustrated in figure 2-1 . the dsp56362 is operated from a 3.3 v supply; however, some of the inputs can tolerate 5 v. a special notice for this feature is added to th e signal descriptions of those inputs. table 2-1 dsp56362 functional signal groupings functional group number of signals detailed description power (v cc )20 table 2-2 ground (gnd) 19 table 2-3 clock and pll 4 table 2-4 address bus port a 1 1 port a is the external memory interface port, including the external address bus, data bus, and control signals. 18 table 2-5 data bus 24 table 2-6 bus control 11 table 2-7 interrupt and mode control 5 table 2-8 hdi08 port b 2 2 port b signals are the gpio port signals which are multiplexed with the hdi08 signals. 16 table 2-9 shi 5 table 2-10 esai port c 3 3 port c signals are the gpio port signals wh ich are multiplexed with the esai signals. 12 table 2-11 digital audio transmitter (dax) port d 4 4 port d signals are the gpio port signals which are multiplexed with the dax signals. 2 table 2-12 timer 1 table 2-13 jtag/once port 6 table 2-14
signal groupings dsp56362 technical data, rev. 4 2-2 freescale semiconductor figure 2-1 signals identified by functional group dsp56362 24 18 external address bus external data bus external bus control serial host interface (shi) timer 0 2 pll jtag/onc e port power inputs: pll external i/o internal logic address bus data bus bus control hdi08 shi/esai/dax/timer a0?a17 d0?d23 aa0?aa3/ ras0 ?ras3 cas rd wr ta br bg bb tck tdi tdo tms trst de clkout pcap pinit/nmi v ccp v ccqh v ccql v cca v ccd v ccc v cch v ccs 4 digital audio transmitter (dax) 2 4 2 2 grounds: pll pll internal logic address bus data bus bus control hdi08 shi/esai/dax/timer gndp gndp1 gnd q gnd a gnd d gnd c gnd h gnd s 4 4 4 2 interrupt/ mode control moda/irqa modb/irqb modc/irqc modd/irqd reset host interface (hdi08) port 1 non-multiplexe d bus h0?h7 ha0 ha1 ha2 hcs/ hcs single ds hrw hds /hds single hr horeq /horeq hack /hack aci ado tio0 8 3 2 extal clock and multiplexed bus had0?had7 has /has ha8 ha9 ha10 double ds hrd/hrd hwr /hwr double hr htrq /htrq hrrq /hrrq port b gpio pb0?pb7 pb8 pb9 pb10 pb13 pb11 pb12 pb14 pb15 port d gpio pd0 pd1 port c gpio pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 timer gpio tio0 port a 4 notes: 1. the hdi08 port supports a nonmultiplexed or a multip lexed bus, single or double data strobe (ds), and single or double host request (hr) conf igurations. since each of these modes is configured independently, any combination of these modes is possible. these hdi08 signals can also be config ured alternately as gpio signals (pb0?pb15). si gnals with dual designations (e.g., has /has) have configurable polarity. 2. the esai signals are multiplexed with the port c gpio signals (pc0?pc11). the dax signals are multiplexed with the port d gpio signals (pd0?pd1). the timer 0 si gnal can be configured alte rnately as the timer gpio signal (tio0). spi mode mosi ss miso sck hreq i 2 c mode ha0 ha2 sda scl hreq enhanced serial audio interface (esai) 2 sckr fsr hckr sckt fst hckt sdo5/sdi0 sdo4/sdi1 sdo3/sdi2 sdo2/sdi3 sdo1 sdo0 3 aa0601
power dsp56362 technical data, rev. 4 freescale semiconductor 2-3 2.2 power table 2-2 power inputs power name description v ccp pll power ?v ccp is v cc dedicated for pll use. the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. there is one v ccp input. v ccql (4) quiet core (low) power? v ccql is an isolated power for the core processing logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccq inputs. v ccqh (3) quiet external (high) power ?v ccqh is a quiet power source for i/o lines. this input must be tied externally to all other chip power inputs. the user must provide adequate decoupling capacitors. there are three v ccqh inputs. v cca (3) address bus power ?v cca is an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip powe r inputs. the user must provide adequate external decoupling capacitors. there are three v cca inputs. v ccd (4) data bus power ?v ccd is an isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccd inputs. v ccc (2) bus control power ?v ccc is an isolated power for the bus control i/o drivers. this input must be tied externally to all other chip power inputs. th e user must provide adequate external decoupling capacitors. there are two v ccc inputs. v cch host power ?v cch is an isolated power for the hdi08 i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there is one v cch input. v ccs (2) shi, esai, dax, and timer power ?v ccs is an isolated power for the shi, esai, dax, and timer i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are two v ccs inputs.
ground dsp56362 technical data, rev. 4 2-4 freescale semiconductor 2.3 ground 2.4 clock and pll table 2-3 grounds ground name description gnd p pll ground ?gnd p is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 f capacitor located as close as possible to the chip package. there is one gnd p connection. gnd p1 pll ground 1 ?gnd p1 is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. there is one gnd p1 connection. gnd q (4) quiet ground ?gnd q is an isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections . the user must provide adequate external decoupling capacitors. there are four gnd q connections. gnd a (4) address bus ground ?gnd a is an isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are four gnd a connections. gnd d (4) data bus ground ?gnd d is an isolated ground for sections of t he data bus i/o drivers. this connection must be tied externally to all other chip ground c onnections. the user must provide adequate external decoupling capacitors. there are four gnd d connections. gnd c (2) bus control ground ?gnd c is an isolated ground for the bus contro l i/o drivers. this connection must be tied externally to all other chip ground conn ections. the user must provide adequate external decoupling capacitors. there are two gnd c connections. gnd h host ground ?gnd h is an isolated ground for the hdi08 i/o drivers. this connection must be tied externally to all other chip ground connections. th e user must provide adequate external decoupling capacitors. there is one gnd h connection. gnd s (2) shi, esai, dax, and timer ground ?gnd s is an isolated ground for t he shi, esai, dax, and timer i/o drivers. this connection must be tied externally to all other chip ground c onnections. the user must provide adequate external decouplin g capacitors. there are two gnd s connections. table 2-4 clock and pll signals signal name type state during reset signal description extal input input external clock input?an external clock source must be connected to extal in order to supply the clock to the internal clock generator and pll. this input cannot tolerate 5v . clkout output chip-driven clock output ?clkout provides an output clock synchronized to the internal core clock phase. if the pll is enabled and both the multiplication and division factors equal one, then clkout is also synchronized to extal. if the pll is disabled, the clkout fr equency is half the frequency of extal. clkout is not functional at frequencies of 100 mhz and above.
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 2-5 2.5 external memory expansion port (port a) when the dsp56362 enters a low-power standby mode (s top or wait), it releas es bus mastership and tri-states the relevant port a signals: a0?a17, d0?d23, aa0/ras0 ?aa3/ras3 , rd , wr , bb , cas . 2.5.1 external address bus 2.5.2 external data bus pcap input input pll capacitor ?pcap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. pinit/nmi input input pll initial/non maskable interrupt ?during assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is enabled or disabled. after reset deassertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered non maskable interrupt (nmi) request internally synchronized to clkout. pinit/nmi cannot tolerate 5 v . table 2-5 external address bus signals signal name type state duri ng reset signal description a0?a17 output tri-stated address bus ?when the dsp is the bus master, a0?a17 are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power dissipation, a0?a17 do not change state when external memory spaces are not being accessed. table 2-6 external data bus signals signal name type state during reset signal description d0?d23 input/output tri-stated data bus ?when the dsp is the bus master, d0?d23 are active-high, bidirectional input/outputs that pr ovide the bidirectional data bus for external program and data memory accesses. otherwise, d0?d23 are tri-stated. table 2-4 clock and pll signals (continued) signal name type state during reset signal description
external memory expansion port (port a) dsp56362 technical data, rev. 4 2-6 freescale semiconductor 2.5.3 external bus control table 2-7 external bus control signals signal name type state during reset signal description aa0?aa3/ra s0 ?ras3 output tri-stated address attribute or row address strobe ?when defined as aa, these signals can be used as chip selects or additional address lines. when defined as ras , these signals can be used as ras for dram interface. these signals are can be tri-stated outputs with programmable polarity. cas output tri-stated column address strobe ?when the dsp is the bus master, cas is an active-low output used by dram to st robe the column address. otherwise, if the bus mastership enable (bme) bit in the dram control register is cleared, the signal is tri-stated. rd output tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d0?d23). otherwise, rd is tri-stated. wr output tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d0?d23). otherwise, the signals are tri-stated. ta input ignored input transfer acknowledge ?if the dsp56362 is the bus master and there is no external bus activity, or the dsp56362 is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle in definitely. any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the bcr by keeping ta deasserted. in typical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to clkout. the number of wait states is determined by the ta input or by the bus control register (bcr), whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. in order to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait st ate access cannot be extended by ta deassertion, otherwise improper operation may result. ta can operate synchronously or asynchronously, depending on the setting of the tas bit in the operating mode register (omr). ta functionality may not be used while performing dram type accesses, otherwise improper operation may result.
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 2-7 br output output (deasserted) bus request ?br is an active-low output, never tri-stated. br is asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br may be asserted or deasserted independent of whether the dsp56362 is a bus master or a bus slave. bus ?parking? allows br to be deasserted even though the dsp56362 is the bus master. (see the description of bus ?parking? in the bb signal description.) the bus request hold (brh) bit in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. br is only affected by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. bg input ignored input bus grant ?bg is an active-low input. bg is asserted by an external bus arbitration circuit when the dsp56362 becomes the next bus master. when bg is asserted, the dsp56362 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may occur in the middle of an instruction that requires more than one external bus cycle for execution. the default mode of operation of this signal requires a setup and hold time referred to clkout. but clkout operation is not guaranteed from 100mhz and up, so the asynchronous bus arbitration must be used for clock frequencies 100mhz and above. the asynchronous bus arbitration is enabled by setting the abe bit in the omr register. bb input/ output input bus busy ?bb is a bidirectional active-low input/output. bb indicates that the bus is active. only after bb is deasserted can the pending bus master become the bus master (and then assert the signal again). the bus master may keep bb asserted after ceasing bus acti vity regardless of whether br is asserted or deasserted. this is called ?bus parking? and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. the deassertion of bb is done by an ?active pull-up? method (i.e., bb is driven high and then released and held high by an external pull-up resistor). the default mode of operation of this signal requires a setup and hold time referred to clkout. but clkout operation is not guaranteed from 100mhz and up, so the asynchronous bus arbitration must be used for clock frequencies 100mhz and above. the asynchronous bus arbitration is enabled by setting the abe bit in the omr register. bb requires an external pull-up resistor. table 2-7 external bus control signals (continued) signal name type state during reset signal description
interrupt and mode control dsp56362 technical data, rev. 4 2-8 freescale semiconductor 2.6 interrupt and mode control the interrupt and mode control signals select the chip?s operating m ode as it comes out of hardware reset. after reset is deasserted, these inputs are hardware interrupt request lines. table 2-8 interrupt and mode control signal name type state duri ng reset signal description moda/irqa input input mode select a/external interrupt request a? moda/irqa is an active-low schmitt-trigger input, internally synchronized to the dsp clock. moda/irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the omr when the reset signal is deasserted. if irqa is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqa to exit the wait state. if the processor is in the stop standby state and the moda/irqa pin is pulled to gnd, the processor will exit the stop state. this input is 5 v tolerant. modb/irqb input input mode select b/external interrupt request b? modb/irqb is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modb/irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. if irqb is asserted synchronous to clkout, multiple processors can be re-synchronized using the wait instruction and asserting irqb to exit the wait state. this input is 5 v tolerant. modc/irqc input input mode select c/external interrupt request c? modc/irqc is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modc/irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. if irqc is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqc to exit the wait state. this input is 5 v tolerant.
host interface (hdi08) dsp56362 technical data, rev. 4 freescale semiconductor 2-9 2.7 host interface (hdi08) the hdi08 provides a fast, 8-bit, para llel data port that may be connect ed directly to the host bus. the hdi08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocesso rs, dsps, and dma hardware. 2.7.1 host port configuration signal functions associated with the hdi08 vary acc ording to the interface operating mode as determined by the hdi08 port control register (hpcr). see 6.5.6 host port control register (hpcr) on page section 6-13 for detailed descri ptions of this register and (see host interface (hdi08) on page section 6-1.) for descriptions of the other hdi08 configuration registers. modd/irqd input input mode select d/external interrupt request d ?modd/irqd is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modd/irqd selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. if irqd is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqd to exit the wait state. this input is 5 v tolerant. reset input input reset? reset is an active-low, schmitt-trigger input. when asserted, the chip is placed in the reset stat e and the internal phase generator is reset. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. if reset is deasserted synchronous to clkout, exact start-up timing is guaranteed, allowing multiple processors to start sync hronously and operate together in ?lock-step.? when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted during power up. a stable extal signal must be supplied while reset is being asserted. this input is 5 v tolerant. table 2-8 interrupt and mode control (continued) signal name type state duri ng reset signal description
host interface (hdi08) dsp56362 technical data, rev. 4 2-10 freescale semiconductor table 2-9 host interface signal name type state during reset signal description h0?h7 had0?had7 pb0?pb7 input/output input/output input, output, or disconnected gpio disconnected host data? when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional, tri-state data bus. host address? when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the address/data bidirectional, multiplexed, tri-state bus. port b 0?7 ?when the hdi08 is configured as gpio, these signals are individually programmable as input, output, or internally disconnected. the default state after reset for these signals is gpio disconnected. this input is 5 v tolerant. ha0 has /has pb8 input input input, output, or disconnected gpio disconnected host address input 0 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus. host address strobe? when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programmable, but is configured active-low (has ) following reset. port b 8 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. ha1 ha8 pb9 input input input, output, or disconnected gpio disconnected host address input 1 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is line 1 of the host address (ha1) input bus. host address 8 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 8 of the host address (ha8) input bus. port b 9 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant.
host interface (hdi08) dsp56362 technical data, rev. 4 freescale semiconductor 2-11 ha2 ha9 pb10 input input input, output, or disconnected gpio disconnected host address input 2 ?when the hdi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 2 of the host address (ha2) input bus. host address 9 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 9 of the host address (ha9) input bus. port b 10 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hrw hrd /hrd pb11 input input input, output, or disconnected gpio disconnected host read/write ?when hdi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host read/write (hrw) input. host read data ?when hdi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host read data strobe (hrd) schmitt-trigger input. the polarity of the data strobe is programmable, but is configured as active-low (hrd ) after reset. port b 11 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hds /hds hwr /hwr pb12 input input input, output, or disconnected gpio disconnected host data strobe? when hdi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host data strobe (hds) schmitt-trigger input. the polarity of the data strobe is pr ogrammable, but is configured as active-low (hds ) following reset. host write data ?when hdi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host write data stro be (hwr) schmitt-trigger input. the polarity of the data strobe is programmable, but is configured as active-low (hwr ) following reset. port b 12 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 2-9 host interface (continued) signal name type state during reset signal description
host interface (hdi08) dsp56362 technical data, rev. 4 2-12 freescale semiconductor hcs ha10 pb13 input input input, output, or disconnected gpio disconnected host chip select? when hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable, but is configured active-low (hcs ) after reset. host address 10 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 10 of the host address (ha10) input bus. port b 13 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 2-9 host interface (continued) signal name type state during reset signal description
host interface (hdi08) dsp56362 technical data, rev. 4 freescale semiconductor 2-13 horeq /hore htrq /htrq pb14 output output input, output, or disconnected gpio disconnected host request ?when hdi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request (horeq) output. the polarity of the host request is programmable, but is configured as active-low (horeq ) following reset. the host request may be programmed as a driven or open-drain output. transmit host request? when hdi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the transmit host request (htrq) output. the polarity of the host request is programmable, but is configured as active-low (htrq ) following reset. the host request may be programmed as a driven or open-drain output. port b 14 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hack /hack hrrq /hrrq pb15 input output input, output, or disconnected gpio disconnected host acknowledge ?when hdi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host acknowledge (hack) schmitt-trigger input. the polarity of the host acknowledge is programmable, but is configured as active-low (hack ) after reset. receive host request ?when hdi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the receive host request (hrrq) output. the polarity of the host request is programmable, but is configured as active-low (hrrq ) after reset. the host request may be programmed as a driven or open-drain output. port b 15 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 2-9 host interface (continued) signal name type state during reset signal description
serial host interface dsp56362 technical data, rev. 4 2-14 freescale semiconductor 2.8 serial host interface the shi has five i/o signals that can be configured to allow the sh i to operate in either spi or i 2 c mode. table 2-10 serial host interface signals signal name signal type state during reset signal description sck scl input or output input or output tri-stated spi serial clock ?the sck signal is an output when the spi is configured as a master and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is st able. edge polarity is determined by the spi transfer protocol. i 2 c serial clock ?scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. miso sda input or output input or open-drain output tri-stated spi master-in-slave-out ?when the spi is configured as a master, miso is the master data input li ne. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when conf igured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is deasserted. an external pull-up resistor is not required for spi operation. i 2 c data and acknowledge ?in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is a unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is a unique situation defined as the stop event. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant.
serial host interface dsp56362 technical data, rev. 4 freescale semiconductor 2-15 mosi ha0 input or output input tri-stated spi master-out-slave-in ?when the spi is configured as a master, mosi is the master dat a output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. i 2 c slave address 0 ?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when configured for the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. ss ha2 input input tri-stated spi slave select ?this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mo de, this signal should be kept deasserted (pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. i 2 c slave address 2 ?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. hreq input or output tri-stated host request ?this signal is an active low schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next da ta word transfer and deasserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this signal is tri-stated during hardware, software, personal reset, or when the hreq1?hreq0 bits in the hcsr are cleared. there is no need for external pull-up in this state. this input is 5 v tolerant. table 2-10 serial host interface signals (continued) signal name signal type state during reset signal description
enhanced serial audio interface dsp56362 technical data, rev. 4 2-16 freescale semiconductor 2.9 enhanced serial audio interface table 2-11 enhanced serial audio interface signals signal name signal type state during reset signal description hckr pc2 input or output input, output, or disconnected gpio disconnected high frequency clock for receiver ?when programmed as an input, this signal provides a high frequency clock source for the esai receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to ana log converters [dacs]) or as an additional system clock. port c 2 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. hckt pc5 input or output input, output, or disconnected gpio disconnected high frequency clock for transmitter ?when programmed as an input, this signal provides a high frequency clock source for the esai transmitter as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additio nal system clock. port c 5 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. fsr pc1 input or output input, output, or disconnected gpio disconnected frame sync for receiver ?this is the receiver frame sync input/output signal. in the asynch ronous mode (syn=0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode ( syn=1), it operates as either the serial flag 1 pin (tebe=0), or as th e transmitter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr register. when configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. port c 1 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant.
enhanced serial audio interface dsp56362 technical data, rev. 4 freescale semiconductor 2-17 fst pc4 input or output input, output, or disconnected gpio disconnected frame sync for transmitter ?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direct ion (tfsd) bit in the esai transmit clock control register (tccr). port c 4 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sckr pc0 input or output input, output, or disconnected gpio disconnected receiver serial clock ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. port c 0 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sckt pc3 input or output input, output, or disconnected gpio disconnected transmitter serial clock ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output us ed by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. port c 3 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sdo5 sdi0 pc6 output input input, output, or disconnected gpio disconnected serial data output 5 ?when programmed as a transmitter, sdo5 is used to transmit data from the tx 5 serial transmit shift register. serial data input 0 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. port c 6 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. table 2-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
enhanced serial audio interface dsp56362 technical data, rev. 4 2-18 freescale semiconductor sdo4 sdi1 pc7 output input input, output, or disconnected gpio disconnected serial data output 4 ?when programmed as a transmitter, sdo4 is used to transmit data from the tx 4 serial transmit shift register. serial data input 1 ?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. port c 7 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sdo3 sdi2 pc8 output input input, output, or disconnected gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3 is used to transmit data from the tx 3 serial transmit shift register. serial data input 2 ?when programmed as a receiver, sdi2 is used to receive serial data into the rx2 serial receive shift register. port c 8 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sdo2 sdi3 pc9 output input input, output, or disconnected gpio disconnected serial data output 2 ?when programmed as a transmitter, sdo2 is used to transmit data from the tx 2 serial transmit shift register. serial data input 3 ?when programmed as a receiver, sdi3 is used to receive serial data into the rx3 serial receive shift register. port c 9 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sdo1 pc10 output input, output, or disconnected gpio disconnected serial data output 1 ?sdo1 is used to transmit data from the tx1 serial transmit shift register. port c 10 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. sdo0 pc11 output input, output, or disconnected gpio disconnected serial data output 0 ?sdo0 is used to transmit data from the tx0 serial transmit shift register. port c 11 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. table 2-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
digital audio interface (dax) dsp56362 technical data, rev. 4 freescale semiconductor 2-19 2.10 digital audio interface (dax) 2.11 timer table 2-12 digital audio interface (dax) signals signal name type state during reset signal description aci pd0 input input, output, or disconnected disconnected audio clock input ?this is the dax clock input. when programmed to use an external clock, this input supplies the dax clock. the external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 fs, 384 fs or 512 fs, respectively). port d 0 ?when the dax is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. ado pd1 output input, output, or disconnected disconnected digital audio data output ?this signal is an audio and non-audio output in the form of aes/ebu, cp 340 and iec958 dat a in a biphase mark format. port d 1 ?when the dax is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. table 2-13 timer signal signal name type state during reset signal description tio0 input or output input timer 0 schmitt-tri gger input/output ?when timer 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 0 control/status register (tcsr0). if tio0 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input but connected it to vcc through a pull-up resistor in order to ensure a stable logic level at the input. this input is 5 v tolerant.
jtag/once interface dsp56362 technical data, rev. 4 2-20 freescale semiconductor 2.12 jtag/once interface table 2-14 jtag/once? interface signal name type state during reset signal description tck input input test clock ?tck is a test clock input signal used to synchronize the jtag test logic. it has an internal pull-up resistor. this input is 5 v tolerant. tdi input input test data input ?tdi is a test data serial input signal used for test instructions and data. tdi is sampled on the rising edge of tck and has an internal pull-up resistor. this input is 5 v tolerant. tdo output tri-stated test data output ?tdo is a test data serial output signal used for test instructions and data. tdo can be tri-st ated and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select ?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. this input is 5 v tolerant. trst input input test reset ?trst is an active-low schmitt-trigger input signal used to asynchronously initialize the test controller. trst has an internal pull-up resistor. the use of trst is not recommended for new designs. it is recommended to leave trst disconnected. this input is 5 v tolerant. de input/output input debug event ?de is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering the debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the debug mode. this signal, when asserted as an input, causes the dsp56300 core to finish the current instruction being executed, save the in struction pipeline information, enter the debug mode, and wait for commands to be entered from the debug serial input line. this signal is asserted as an output for three clock cycles when the chip enters the debug mode as a result of a debug request or as a result of meeting a breakpoint condition. the de has an internal pull-up resistor. this is not a standard part of the jt ag tap controller. the signal connects directly to the once module to initiate debug mode directly or to provide a direct external indication that the chip has entered the debug mode. all other interface with the once module must occur through the jtag port. the use of de is not recommended for new designs. it is recommended to leave de disconnected. this input is not 5 v tolerant.
dsp56362 technical data, rev. 4 freescale semiconductor 3-1 3 specifications 3.1 introduction the dsp56362 is fabricated in high density cmos wi th transistor-transistor logic (ttl) compatible inputs and outputs. the dsp56362 spec ifications are prelim inary and are from design simulations, and may not be fully tested or guarantee d. finalized specifications will be published after full characterization and device qualificat ions are complete. 3.2 maximum ratings caution this device contains circuitry protecti ng against damage due to high static voltage or electrical fields. however, normal preca utions should be taken to avoid exceeding maximum voltage ra tings. reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 k ? . note in the calculation of timing requireme nts, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculat ed using a worst case variation of process parameter valu es in one direction. the minimum specification is calculated using the wo rst case for the same parameters in the opposite direction. therefore, a ?m aximum? value for a specification will never occur in the sa me device that has a ?m inimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. table 3-1 maximum ratings rating 1 symbol value 1 , 2 unit supply voltage v cc ? 0.3 to +4.0 v all input voltages excluding ?5 v tolerant? inputs 3 v in gnd ? 0.3 to v cc + 0.3 v all ?5 v tolerant? input voltages 3 v in5 gnd ? 0.3 to v cc + 3.95 v current drain per pin excluding v cc and gnd i 10 ma
thermal characteristics dsp56362 technical data, rev. 4 3-2 freescale semiconductor 3.3 thermal characteristics 3.4 dc electrical characteristics operating temperature range t j ? 40 to +105 c storage temperature t stg ? 55 to +125 c 1 gnd = 0 v, v cc = 3.3 v .16 v, t j = 0c to +100c, c l = 50 pf 2 absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 caution : all ?5 v tolerant? input voltages must not be more than 3. 95 v greater than the supply voltage; this restriction applies to ?power on?, as well as during normal operation. in any case, the input voltages cannot be more than 5.75 v. ?5 v tolerant? inputs are inputs that tolerate 5 v. table 3-2 thermal characteristics characteristic symbo llqfp value unit junction-to-ambient thermal resistance 1 1 junction-to-ambient thermal resistance is based on measurement s on a horizontal single-sided printed circuit board per semi g38-87 in natural convection.(semi is semiconductor equipmen t and materials international, 805 east middlefield rd., mountain view, ca 94043, (415) 964-5111. measurements were done with parts mounted on thermal te st boards conforming to specification eia/jesd51-3. r ja or ja 45.3 c/w junction-to-case thermal resistance 2 2 junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88, with the exception that the cold plate temperature is used for the case temperature. r jc or jc 10.1 c/w thermal characterization parameter jt 5.5 c/w table 3-3 dc electrical characteristics 1 characteristics symbol min typ max unit supply voltage v cc 3.14 3.3 3.46 v input high voltage d(0:23), bg , bb , ta , de , and pinit/nmi mod 2 /irq 2 , reset , and tck/tdi/tms/ trst /esai/timer/hdi08/ shi( spi mode ) pins shi( i2c mode ) pins extal 3 v ih v ihp v ihx 2.0 2.0 1.5 0.8 v cc ? ? ? v cc v cc + 3.95 v cc + 3.95 v cc v input low voltage d(0:23), bg , bb , ta , mod 2 /irq 2 , reset , pinit/nmi all jtag/esai/t imer/hdi08/ shi( spi mode ) pins shi( i2c mode ) pins extal 3 v il v ilp v ilx ?0.3 ?0.3 ?0.3 ?0.3 ? ? ? 0.8 0.8 0.3 v cc 0.2 v cc v table 3-1 maximum ratings (continued) rating 1 symbol value 1 , 2 unit
ac electrical characteristics dsp56362 technical data, rev. 4 freescale semiconductor 3-3 3.5 ac electrical characteristics the timing waveforms shown in th e ac electrical characteristics section are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except extal, which is tested using the input levels shown in note 6 of the previous ta ble. ac timing specificat ions, which are referenced to a device input signal, are measured in production with respect to th e 50% point of the respective input signal's transition. dsp56362 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. note although the minimum value for the frequency of extal is 0 mhz, the device ac test conditions are 15 mhz and rated speed. input leakage current i in ?10 ? 10 a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi ?10 ? 10 a output high voltage ttl (i oh = ?0.4 a) 4, 5 cmos (i oh = ?10 a) 4 v oh 2.4 v cc ? 0.01 ? ?? v output low voltage ttl (i ol = 3.0 a, open-drain pins i ol = 6.7 a) 4, 5 cmos (i ol = 10 a) 4 v ol ?? 0.4 0.01 v internal supply current 6 (operating frequency 100mhz for current measurements) in normal mode in wait mode in stop mode 7 i cci i ccw i ccs ? ? ? 127 7. 5 100 181 11 150 a pll supply current ? 1 2.5 a input capacitance 4 c in ? ? 10 pf 1 v cc = 3.3 v 5% v; t j = 0c to +100c, c l = 50 pf 2 refers to moda/irqa , modb/irqb , modc/irqc , and modd/irqd pins. 3 driving extal to the low v ihx or the high v ilx value may cause additional power consumption (dc current). to minimize power consumption, the minimum v ihx should be no lower than 0.9 v cc and the maximum v ilx should be no higher than 0.1 v cc . 4 periodically sampled and not 100% tested. 5 this characteristic does not apply to pcap. 6 section 5.3, "power consum ption considerations" provides a formula to compute the estimated current requirements in normal mode. in order to obtain these result s, all inputs must be terminated (i.e., not allowed to float). measurements are based on synthetic int ensive dsp benchmarks. the power consumpti on numbers in this specification are 90% of the measured results of this benchmark. this reflects typical dsp applications. typical internal supply current is measured with v cc = 3.3 v at t j = 100c. maximum internal supply current is measured with v cc = 3.46 v at t j = 100c. 7 in order to obtain these results, all inputs, which are not disco nnected at stop mode, must be terminated (i.e., not allowed to float). table 3-3 dc electrical characteristics 1 (continued) characteristics symbol min typ max unit
internal clocks dsp56362 technical data, rev. 4 3-4 freescale semiconductor 3.6 internal clocks table 3-4 internal clocks, clkout characteristics symbol expression 1 , 2 1 df = division factor ef = external frequency et c = external clock cycle mf = multiplication factor pdf = predivision factor t c = internal clock cycle 2 see the pll and clock generation section in the dsp56300 family manual for a detailed discussion of the pll. min typ max internal operation frequency and clkout with pll enabled f?(ef mf)/(pdf df) ? internal operation frequency and clkout with pll disabled f? ef/2 ? internal clock and clkout high period with pll disabled with pll enabled and mf 4 with pll enabled and mf > 4 t h ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock and clkout low period with pll disabled with pll enabled and mf 4 with pll enabled and mf > 4 t l ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock and clkout cycle time with pll enabled t c ?et c pdf df/mf ? internal clock and clkout cycle time with pll disabled t c ?2 et c ? instruction cycle time i cyc ?t c ?
external clock operation dsp56362 technical data, rev. 4 freescale semiconductor 3-5 3.7 external clock operation the dsp56362 system clock is an ex ternally supplied square wave vol tage source connected to extal ( figure 3-1 ) figure 3-1 external clock timing table 3-5 clock operation 100 and 120 mhz values no. characteristics symbol 100 mhz 120 mhz min max min max 1 frequency of extal (extal pin frequency) the rise and fall time of this external clock should be 3 ns maximum. ef 0 100.0 0 120.0 2 extal input high 1, 2 with pll disabled (46.7%?53.3% duty cycle) 3 with pll enabled (42.5%?57.5% duty cycle) 3 et h 4.67 ns 4.25 ns 157.0 s 0.00 ns 0.00 ns 157.0 s 3 extal input low 1, 2 with pll disabled (46.7%?53.3% duty cycle) 3 with pll enabled (42.5%?57.5% duty cycle) 3 et l 4.67 ns 4.25 ns 157.0 s 4.67 ns 4.25 ns ? 1570.00 4 extal cycle time 2 with pll disabled with pll enabled et c 10.00 ns 10.00 ns 273.1 s 8.33 ns 8.33 ns ? 273.1 s 5 clkout change from extal fall with pll disabled 4.3 ns 11.0 ns extal v ilc v ihc midpoint note: the midpoint is 0.5 (v ihc + v ilc ). eth etl etc clkout with pll disabled clkout with pll enabled 7 5 7 6b 5 3 4 2 aa0459 6a
phase lock loop (pll) characteristics dsp56362 technical data, rev. 4 3-6 freescale semiconductor 3.8 phase lock loop (pll) characteristics 6 clkout rising edge from extal rising edge with pll enabled (mf = 1, pdf = 1, ef > 15 mhz) 4, 5 clkout falling edge from extal rising edge with pll enabled (mf = 2 or 4, pdf = 1, ef > 15 mhz) 4, 5 clkout falling edge from extal falling edge with pll enabled (mf 4, pdf 1, ef / pdf > 15 mhz) 4, 5 0.0 ns 0.0 ns 0.0 ns 1.8 ns 1.8 ns 1.8 ns 7 instruction cycle time = i cyc = t c 6 see table 3-5 (46.7%?53.3% duty cycle) with pll disabled with pll enabled i cyc 0.00 ns 0.00 ns 8.53 s 8.53 s 1 measured at 50% of the input transition. 2 the maximum value for pll enabled is given for minimum v co and maximum mf. 3 the indicated duty cycle is for t he specified maximum frequency for which a part is rated. th e minimum clock high or low time required for correction operation, however, remains the sa me at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from th e specified duty cycle as long as the minimum high time and low time requirements are met. 4 periodically sampled and not 100% tested. 5 the skew is not guaranteed for any other mf value. 6 the maximum value for pll enabled is given for minimum v co and maximum df. table 3-6 pll characteristics characteristics 100 mhz unit min max v co frequency when pll enabled (mf e f 2/pdf) 30 200 mhz pll external capacitor (pcap pin to v ccp ) (c pcap ) 1 @ mf 4 @ mf > 4 1 c pcap is the value of the pll capacitor (connected between the pcap pin and v ccp ). the recommended value in pf for c pcap can be computed from one of the following equations: (680 mf) ? 120, for mf 4, or 1100 mf, for mf > 4 (mf 580) ? 100 mf 830 (mf 780) ? 140 mf 1470 pf pf note: table 3-5 clock operation (continued) 100 and 120 mhz values no. characteristics symbol 100 mhz 120 mhz min max min max
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 freescale semiconductor 3-7 3.9 reset, stop, mode select, and interrupt timing table 3-7 reset, stop, mode select, and interrupt timing 100 and 120 mhz values 1 no characteristics expression 2 100 mhz 120 mhz unit min max min max 8 delay from reset assertion to all pins at reset value 3 ? ? 26.0 26.0 ns 9 required reset duration 4 power on, external clock generator, pll disabled power on, external clock generator, pll enabled power on, internal oscillator during stop, xtal disabled (pctl bit 16 = 0) during stop, xtal enabled (pctl bit 16 = 1) during normal operation 50 et c 1000 et c 75000 et c 75000 et c 2.5 t c 2.5 t c 500.0 10.0 750 750 25.0 25.0 ? ? ? ? ? ? 416.7 8.3 625 625 20.8 20.8 ? ? ? ? ? ? ns s s s ns ns 10 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) 5 minimum maximum 3.25 t c + 2.0 20.25 t c + 7.50 34.5 ? ? 211.5 29.1 176.2 ns ns 11 synchronous reset setup time from reset deassertion to clkout transition 1 minimum maximum t c 5.9 ? ? 10.0 ns ns 12 synchronous reset deasserted, delay time from the clkout transition 1 to the first external address output minimum maximum 3.25 t c + 2.0 20.25 t c + 7.5 33.5 ? ? 207.5 ns ns 13 mode select setup time 30.0 ? 30.0 ns 14 mode select hold time 0.0 ? 0.0 ns 15 minimum edge-triggered interrupt request assertion width 6.6 ? 5.5 ns 16 minimum edge-triggered interrupt request deassertion width 6.6 ? 5.5 ns 17 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory access address out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 4.25 t c + 2.0 7.25 t c + 2.0 44.5 74.5 ? ? 37.4 62.4 ns ns 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 t c + 5.0 105.0 ? 88.3 ns
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 3-8 freescale semiconductor 19 delay from address output valid caused by first interrupt instruction execute to interr upt request deassertion for level sensitive fast interrupts 6 (3.75 + ws) t c ? 10.94 ?note 7 ?note 7ns 20 delay from rd assertion to in terrupt request deassertion for level sensitive fast interrupts 6 (3.25 + ws) t c ? 10.94 ? note 7 ? note 7 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 6 8 dram for all ws sram ws =1 sram ws=2, 3 sram ws 4 (ws + 3.5) t c ? 10.94 (ws + 3.5) t c ? 10.94 1.75 t c ? 4.0 2.75 t c ? 4.0 ? ? ? ? note 7 note 7 note 7 note 7 ? ? ? ? note 7 note 7 note 7 note 7 ns ns ns ns 22 synchronous interrupt setup time from irqa , irqb , irqc , irqd , nmi assertion to the clkout transition 2 0.6 t c ? 0.1 5.9 4.9 ? ns 23 synchronous interrupt delay time from the clkout transition 2 to the first external address output valid caused by the first instruct ion fetch after coming out of wait processing state minimum maximum 9.25 t c + 1.0 24.75 t c + 5.0 93.5 ? ? 252.5 78.1 ? ? 211.2 ns ns 24 duration for irqa assertion to recove r from stop state 0.6 t c ? 0.1 5.9 ? 4.9 ? ns 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 9, 3 pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128 k ? plc/2) t c plc et c pdf + (23.75 0.5) t c (8.25 0.5) t c 1.3 232.5 ns 77.5 13.6 12.3 ms 87.5 ? ? 64.6 ? ? 72.9 ms ns 26 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 9, 3 pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128k ? plc/2) t c plc et c pdf + (20.5 0.5) t c 5.5 t c 13.6 12.3 55.0 ? ? ?45.8? ms ms ns table 3-7 reset, stop, mode select, and interrupt timing 100 and 120 mhz values 1 (continued) no characteristics expression 2 100 mhz 120 mhz unit min max min max
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 freescale semiconductor 3-9 27 interrupt requests rate hi08, esai, shi, timer dma irq , nmi (edge trigger) irq , nmi (level trigger) 12t c 8t c 8t c 12t c ? ? ? ? 120.0 80.0 80.0 120.0 ? ? ? ? 100.0 66.7 66.7 100.0 ns ns ns ns 28 dma requests rate data read from hi08, esai, shi data write to hi08, esai, shi timer irq , nmi (edge trigger) 6t c 7t c 2t c 3t c ? ? ? ? 60.0 70.0 20.0 30.0 ? ? ? ? 50.0 58.0 16.7 25.0 ns ns ns ns 29 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory (dma source) access address out valid 4.25 t c + 2.0 44.0 ? 37.4 ? ns 1 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf 2 use expression to compute maximum value. 3 periodically sampled and not 100% tested. 4 for an external clock generator, reset duration is measured during the time in which reset is asserted, v cc is valid, and the extal input is active and valid. for internal oscillator, reset duration is measured duri ng the time in which reset is asserted and v cc is valid. the specified timing reflects the crystal oscillator stabilization time after power-up . this number is affected both by the specifications of the crystal and other components connecte d to the oscillator and reflects worst case conditions. when the v cc is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. designs should minimi ze this state to the shortest possible duration. 5 if pll does not lose lock. 6 when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restri ctions, the deasserted edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. 7 these values depend on the number of wait states (ws) selected. 8 ws = number of wait states (meas ured in clock cycles, number of t c. 9 this timing depends on several settings: for pll disable, using in ternal oscillator (pll control r egister (pctl) bit 16 = 0) an d oscillator disabled during stop (pctl bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. in that case, resetting the stop delay (omr bit 6 = 0) will provide the proper delay. while it is possible to set omr bit 6 = 1, it is not recommended and these spec ifications do not guarantee timings for that case. for pll disable, using internal oscillator (pctl bit 16 = 0) a nd oscillator enabled during stop (pctl bit 17=1), no stabilizati on delay is required and recovery time will be minimal (omr bit 6 setting is ignored). for pll disable, using external clock (pctl bit 16 = 1), no stabilization delay is required and recovery time will be defined b y the pctl bit 17 and omr bit 6 settings. for pll enable, if pctl bit 17 is 0, the pll is shutdown during stop. recovering fr om stop requires the pll to get locked. the pll lock procedure duration, pll lock cycles (plc), may be in the range of 0 to 1000 cycles. this procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. the stop delay counter completes count or pll lock procedure completion. plc value for pll disable is 0. the maximum value for et c is 4096 (maximum mf) divided by the desired internal frequency (i.e., for 100 mhz it is 4096/100 mhz = 40.96 s). during the stabilization period, t c , t h, and t l will not be constant, and their width may vary, so timing may vary as well. table 3-7 reset, stop, mode select, and interrupt timing 100 and 120 mhz values 1 (continued) no characteristics expression 2 100 mhz 120 mhz unit min max min max
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 3-10 freescale semiconductor figure 3-2 reset timing figure 3-3 synchronous reset timing v ih reset reset value first fetch all pins a0?a17 8 9 10 aa0460 clkout reset a0?a17 11 12 aa0461
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 freescale semiconductor 3-11 figure 3-4 external fast interrupt timing figure 3-5 external interrupt ti ming (negative edge-triggered) a0?a17 rd a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general purpose i/o irqa , irqb , irqc , irqd , nmi wr 20 21 19 17 18 aa0462 first interrupt instruction execution/fetch irqa , irqb , irqc , irqd , nmi irqa , irqb , irqc , irqd , nmi 15 16 aa0463
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 3-12 freescale semiconductor figure 3-6 synchronous interrupt from wait state timing figure 3-7 operating mode select timing figure 3-8 recovery from stop state using irqa clkout irqa , irqb , irqc , irqd , nmi a0?a17 22 23 aa0464 reset moda , modb , modc , modd , pinit v ih irqa , irqb , irqc , irqd , nmi v ih v il v ih v il 13 14 aa0465 first instruction fetch irqa a0?a17 24 25 aa0466
reset, stop, mode select, and interrupt timing dsp56362 technical data, rev. 4 freescale semiconductor 3-13 figure 3-9 recovery from stop state using irqa interrupt service figure 3-10 external memory access (dma source) timing irqa a0?a17 first irqa interrupt instruction fetch 26 25 aa0467 29 dma source address first interrupt instruction execution a0?a17 rd wr irqa , irqb , irqc , irqd , nmi aa1104
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-14 freescale semiconductor 3.10 external memory expansion port (port a) 3.10.1 sram timing table 3-8 sram read and write accesses 100 and 120 mhz 1 no. characteristics symbol expression 2 100 mhz 120 mhz unit min max min max 100 address valid and aa assertion pulse width 3 t rc , t wc (ws + 1) t c ? 4.0 [1 ws 3] 16.0 ? 12.0 ? ns (ws + 2) t c ? 4.0 [4 ws 7] 56.0 ? 46.0 ? ns (ws + 3) t c ? 4.0 [ws 8] 106.0 ? 87.0 ? ns 101 address and aa valid to wr assertion t as 100 mhz: 0.25 t c ? 2.0 [ws = 1] 0.5 ? 0.1 ? ns 1.25 t c ? 2.0 [ws 4] 10.5 ? 8.4 ? ns 102 wr assertion pulse width t wp 100 mhz: 1.5 t c ? 4.0 [ws = 1] 11.0 ? 8.5 ? ns all frequencies: ws t c ? 4.0 [2 ws 3] 16.0 ? 12.7 ? ns (ws ? 0.5) t c ? 4.0 [ws 4] 31.0 --- 25.2 ? 103 wr deassertion to address not valid t wr 100 mhz: 0.25 t c ? 2.0 [1 ws 3] 0.5 ? 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 10.5 ? 8.4 ? 2.25 t c ? 2.0 [ws 8] 20.5 ? 16.7 ? all frequencies: 1.25 t c ? 4.0 [4 ws 7] 8.5 ? 6.4 ? 2.25 t c ? 4.0 [ws 8] 18.5 ? 14.7 ?
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-15 104 address and aa valid to input data valid t aa , t ac 100 mhz: (ws + 0.75) t c ? 7.0 [ws 1] ? 10.5 7.6 ns 105 rd assertion to input data valid t oe 100 mhz: (ws + 0.25) t c ? 7.0 [ws 1] ?5.5?3.4ns 106 rd deassertion to data not valid (data hold time) t ohz 0.0 ? 0.0 ? ns 107 address valid to wr deassertion 3 t aw (ws + 0.75) t c ? 4.0 [ws 1] 13.5 ? 10.6 ? ns 108 data valid to wr deassertion (data setup time) t ds (t dw ) 100 mhz: (ws ? 0.25) t c ? 3.0 [ws 1] 4.5 ? 3.2 ? ns 109 data hold time from wr deassertion t dh 100 mhz: 0.25 t c ? 2.0 [1 ws 3] 0.5 ? 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 10.5 ? 8.4 ? 2.25 t c ? 2.0 [ws 8] 20.5 ? 16.7 ? 110 wr assertion to data active 4 0.75 t c ? 3.7 [ws = 1] ??2.5?ns 0.25 t c ? 3.7 [2 ws 3] ??0.0? ? 0.25 t c ? 3.7 [ws 4] ??0.0? 111 wr deassertion to data high impedance 4 0.25 t c + 0.2 [1 ws 3] ???2.3ns 1.25 t c + 0.2 [4 ws 7] ???10.6 2.25 t c + 0.2 [ws 8] ???18.9 table 3-8 sram read and write accesses 100 and 120 mhz 1 (continued) no. characteristics symbol expression 2 100 mhz 120 mhz unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-16 freescale semiconductor 112 previous rd deassertion to data active (write) 4 1.25 t c ? 4.0 [1 ws 3] ??6.4?ns 2.25 t c ? 4.0 [4 ws 7] ??14.7? 3.25 t c ? 4.0 [ws 8] ??23.1? 113 rd deassertion time 100 mhz: 0.75 t c ? 4.0 [1 ws 3] 3.5 ? 2.2 ? ns 1.75 t c ? 4.0 [4 ws 7] 13.5 ? 10.6 ? 2.75 t c ? 4.0 [ws 8] 23.5 ? 18.9 ? 114 wr deassertion time 100 mhz: 0.5 t c ? 4.0 [ws = 1] 1.0 ? 0.2 ? ns t c ? 2.0 [2 ws 3] 6.0 ? 6.3 ? 2.5 t c ? 4.0 [4 ws 7] 21.0 ? 16.8 ? 3.5 t c ? 4.0 [ws 8] 31.0 ? 25.2 ? 115 address valid to rd assertion 100 mhz: 0.5 t c ? 4.0 1.0 ? 0.2 ? ns 116 rd assertion pulse width 100 mhz: (ws + 0.25) t c ? 4.0 8.5 ? 6.4 ? ns 117 rd deassertion to address not valid 100 mhz: 0.25 t c ? 2 .0 [1 ws 3] 0.5 ? 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 10.5 ? 8.4 ? 2.25 t c ? 2.0 [ws 8] 20.5 ? 16.7 ? table 3-8 sram read and write accesses 100 and 120 mhz 1 (continued) no. characteristics symbol expression 2 100 mhz 120 mhz unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-17 figure 3-11 sram read access 118 ta setup before rd or wr deassertion 5 0.25 t c + 2.0 4.5 ? 4.1 ? ns 119 ta hold after rd or wr deassertion 0 ? 0.0 ? ns 1 all timings for 100 mhz are measured from 0.5 vcc to .05 vcc 2 ws is the number of wait states specified in the bcr. 3 timings 100, 107 are guaranteed by design, not tested. 4 timing 110, 111, and 112, ar e not specified for 100 mhz. 5 in the case of ta negation: timing 118 is relative to the deassertion edge of rd or wr were ta to remain active. table 3-8 sram read and write accesses 100 and 120 mhz 1 (continued) no. characteristics symbol expression 2 100 mhz 120 mhz unit min max min max a0?a17 rd wr d0?d23 aa0?aa3 115 105 106 113 104 116 117 100 aa0468 ta 119 data in 118
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-18 freescale semiconductor figure 3-12 sram write access 3.10.2 dram timing the selection guides provided in figure 3-13 and figure 3-16 should be used for primary selection only. final selection should be ba sed on the timing provided in the following tables. as an example, the selection guide suggests that 4 wait states must be used for 100 mhz operation when using page mode dram. however, by using the information in the appropriat e table, a designer may choose to evaluate whether fewer wait states mig ht be used by determining which timing pr events operation at 100 mhz, running the chip at a slightly lower frequency (e.g., 95 mhz), using faster dram (if it become s available), and control factors such as capacitive and resistive lo ad to improve overall system performance. a0?a17 wr rd data out d0?d23 aa0?aa3 100 102 101 107 114 110 112 111 108 109 aa0469 103 ta 119 118
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-19 figure 3-13 dram page mode wait states selection guide table 3-9 dram page mode timings, one wait state (low-power applications) 1, 2, 3 no. characteristics symbol expression 20 mhz 4 30 mhz 4 unit min max min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses. t pc 2 t c 1.25 x tc 100.0 62.5 ? ? 66.7 41.7 ? ? ns 132 cas assertion to data valid (read) t cac t c ? 7.5 ? 42.5 ? 25.8 ns 133 column address valid to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 2 t c ? 4.0 96.0 ? 62.7 ? ns chip frequency (mhz) dram type (trac ns) 100 80 70 60 40 66 80 100 1 wait states 2 wait states 3 wait states 4 wait states note: this figure should be used for primary selection. for exact and detailed timings see the following tables. aa0472 50 120
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-20 freescale semiconductor 137 cas assertion pulse width t cas 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 138 last cas deassertion to ras deassertion 5 brw[1:0] = 00 brw[1:0] = 01 brw[1:0] = 10 brw[1:0] = 11 t crp 1.75 t c ? 6.0 3.25 t c ? 6.0 4.25 t c ? 6.0 6.25 t c ? 6.0 81.5 156.5 206.5 306.5 ? ? ? ? 52.3 102.2 135.5 202.1 ? ? ? ? ns 139 cas deassertion pulse width t cp 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 140 column address valid to cas assertion t asc 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 141 cas assertion to colu mn address not valid t cah 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 142 last column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 143 wr deassertion to cas assertion t rcs 0.75 t c ? 3.8 33.7 ? 21.2 ? ns 144 cas deassertion to wr assertion t rch 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 145 cas assertion to wr deassertion t wch 0.5 t c ? 4.2 20.8 ? 12.5 ? ns 146 wr assertion pulse widt h t wp 1.5 t c ? 4.5 70.5 ? 45.5 ? ns 147 last wr assertion to ras deassertion t rwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 148 wr assertion to cas deassertion t cwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 4.0 8.5 ? 4.3 ? ns 150 cas assertion to data not valid (write) t dh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 151 wr assertion to cas assertion t wcs t c ? 4.3 45.7 ? 29.0 ? ns 152 last rd assertion to ras deassertion t roh 1.5 t c ? 4.0 71.0 ? 46.0 ? ns 153 rd assertion to data valid t ga t c ? 7.5 ? 42.5 ? 25.8 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 156 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 2 t c for read-after-read or write-after-write sequences). 4 reduced dsp clock speed allows use of page mode dram with one wait state. see figure 3-13 . 5 brw[1:0] (dram control register bits) defines the number of wait states that should be inserted in each dram out-of-page access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-9 dram page mode timings, on e wait state (low-power applications) 1, 2, 3 (continued) no. characteristics symbol expression 20 mhz 4 30 mhz 4 unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-21 table 3-10 dram page mode timings, two wait states 1, 2, 3, 4 no. characteristics symbol expression 80 mhz unit min max 131 page mode cycle time for two consecutive accesses of the same direction 5 page mode cycle time for mixed (read and write) accesses. 5 t pc 3 t c 2.75 x tc 37.5 34.4 ? ? ns 132 cas assertion to data valid (read) t cac 1.5 t c ? 6.5 ? 12.3 ns 133 column address valid to data valid (read) t aa 2.5 t c ? 6.5 ? 24.8 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 17.9 ? ns 136 previous cas deassertion to ras deassertion t rhcp 3.25 t c ? 4.0 36.6 ? ns 137 cas assertion pulse width t cas 1.5 t c ? 4.0 14.8 ? ns 138 last cas deassertion to ras deassertion 6 brw[1:0] = 00 brw[1:0] = 01 brw[1:0] = 10 brw[1:0] = 11 t crp 2.0 t c ? 6.0 3.5 t c ? 6.0 4.5 t c ? 6.0 6.5 t c ? 6.0 19.0 37.8 50.3 75.3 ? ? ? ? ns 139 cas deassertion pulse width t cp 1.25 t c ? 4.0 11.6 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 8.5 ? ns 141 cas assertion to column address not valid t cah 1.75 t c ? 4.0 17.9 ? ns 142 last column address valid to ras deassertion t ral 3 t c ? 4.0 33.5 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 3.8 11.8 ? ns 144 cas deassertion to wr assertion t rch 0.5 t c ? 3.7 2.6 ? ns 145 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 14.6 ? ns 146 wr assertion pulse width t wp 2.5 t c ? 4.5 26.8 ? ns 147 last wr assertion to ras deassertion t rwl 2.75 t c ? 4.3 30.1 ? ns 148 wr assertion to cas deassertion t cwl 2.5 t c ? 4.3 27.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 3.0 0.1 ? ns 150 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 17.9 ? ns 151 wr assertion to cas assertion t wcs t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 2.5 t c ? 4.0 27.3 ? ns
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-22 freescale semiconductor 153 rd assertion to data valid t ga 1.75 t c ? 6.5 ? 15.4 ns 154 rd deassertion to data not valid 7 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 9.1 ? ns 156 wr deassertion to data high impedance 0.25 t c ?3.1ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for dsp56362. 4 all the timings are calculated for the worst case. some of the timings are better fo r specific cases (e.g., t pc equals 3 t c for read-after-read or write-after-write sequences). 5 there are not any fast enough drams to fit to two wait states page mode @ 100mhz. see figure 3-13 . 6 brw[1:0] (dram control register bits) defi nes the number of wait states that shou ld be inserted in each dram out-of-page access. 7 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz. table 3-11 dram page mode timings, three wait states 1, 2, 3, 4 no. characteristics symbol expression 100 mhz unit min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mix ed (read and write) accesses. t pc 4 t c 3.5 x tc 40.0 35.0 ? ? ns 132 cas assertion to data valid (read) t cac 100 mhz : 2 t c ? 7.0 ? 13.0 ns 133 column address valid to data valid (read) t aa 100 mhz : 3 t c ? 7.0 ? 23.0 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 2.5 t c ? 4.0 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 4.5 t c ? 4.0 41.0 ? ns 137 cas assertion pulse width t cas 2 t c ? 4.0 16.0 ? ns 138 last cas deassertion to ras assertion 5 brw[1:0] = 00 brw[1:0] = 01 brw[1:0] = 10 brw[1:0] = 11 t crp 2.25 t c ? 6.0 3.75 t c ? 6.0 4.75 t c ? 6.0 6.75 t c ? 6.0 ? ? 41.5 61.5 ? ? ? ? ns table 3-10 dram page mode timings, two wait states 1, 2, 3, 4 (continued) no. characteristics symbol expression 80 mhz unit min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-23 139 cas deassertion pulse width t cp 1.5 t c ? 4.0 11.0 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? ns 141 cas assertion to column address not valid t cah 2.5 t c ? 4.0 21.0 ? ns 142 last column address valid to ras deassertion t ral 4 t c ? 4.0 36.0 ? ns 143 wr deassertion to cas assertion t rcs 100 mhz : 1.25 t c ? 4.0 8.5 ns 144 cas deassertion to wr assertion t rch 100 mhz : 0.75 t c ? 4.0 3.5 ns 145 cas assertion to wr deassertion t wch 2.25 t c ? 4.2 18.3 ? ns 146 wr assertion pulse width t wp 3.5 t c ? 4.5 30.5 ? ns 147 last wr assertion to ras deassertion t rwl 3.75 t c ? 4.3 33.2 ? ns 148 wr assertion to cas deassertion t cwl 3.25 t c ? 4.3 28.2 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 1.0 ? ns 150 cas assertion to data not valid (write) t dh 2.5 t c ? 4.0 21.0 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 3.5 t c ? 4.0 31.0 ? ns 153 rd assertion to data valid t ga 100 mhz : 2.5 t c ? 7.0 ? 18.0 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.5ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for dsp56362. 4 all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 4 t c for read-after-read or write-after-write sequences). 5 brw[1:0] (dram control register bits) defin es the number of wait states that sh ould be inserted in each dram out-of page-access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-11 dram page mode timings, three wait states 1, 2, 3, 4 (continued) no. characteristics symbol expression 100 mhz unit min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-24 freescale semiconductor table 3-12 dram page mode timings, four wait states 100 and 120mhz 1, 2, 3, 4 no. characteristics symbol expression 100 mhz 120 mhz unit min max min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses. t pc 5 t c 4.5 t c 50.0 45.0 ? ? 41.7 37.5 ns 132 cas assertion to data valid (read) t cac 100 mhz : 2.75 t c ? 7.0 ? 20.5 ? 15.9 ns 133 column address valid to data valid (read) t aa 100 mhz : 3.75 t c ? 7.0 ? 30.5 ? 24.2 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 3.5 t c ? 4.0 31.0 ? 25.2 ? ns 136 previous cas deassertion to ras deassertion t rhcp 6 t c ? 4.0 56.0 ? 46.0 ? ns 137 cas assertion pulse width t cas 2.5 t c ? 4.0 21.0 ? 16.8 ? ns 138 last cas deassertion to ras assertion 5 brw[1:0] = 00 brw[1:0] = 01 brw[1:0] = 10 brw[1:0] = 11 t crp 2.75 t c ? 6.0 4.25 t c ? 6.0 5.25 t c ? 6.0 7.25 t c ? 6.0 ? ? 46.5 66.5 ? ? ? ? ? ? 37.7 54.4 ? ? ? ? ns 139 cas deassertion pulse width t cp 2 t c ? 4.0 16.0 ? 12.7 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? 4.3 ? ns 141 cas assertion to column address not valid t cah 3.5 t c ? 4.0 31.0 ? 25.2 ? ns 142 last column address valid to ras deassertion t ral 5 t c ? 4.0 46.0 ? 37.7 ? ns 143 wr deassertion to cas assertion t rcs 100 mhz : 1.25 t c ? 4.0 8.5 ? 6.4 ? ns 144 cas deassertion to wr assertion t rch 100 mhz : 1.25 t c ? 4.0 8.5 ? 6.4 ? ns 145 cas assertion to wr deassertion t wch 3.25 t c ? 4.2 28.3 ? 22.9 ? ns 146 wr assertion pulse width t wp 4.5 t c ? 4.5 40.5 ? 33.0 ? ns 147 last wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 43.2 ? 35.3 ? ns 148 wr assertion to cas deassertion t cwl 3.75 t c ? 4.3 33.2 ? 26.9 ? ns
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-25 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 1.0 ? 0.2 ? ns 150 cas assertion to data not valid (write) t dh 3.5 t c ? 4.0 31.0 ? 25.2 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? 6.1 ? ns 152 last rd assertion to ras deassertion t roh 4.5 t c ? 4.0 41.0 ? 33.5 ? ns 153 rd assertion to data valid t ga 100 mhz : 3.25 t c ? 7.0 ? 25.5 ? 20.1 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 7.2 ? 5.9 ns 156 wr deassertion to data high impedance 0.25 t c ? 2.5 ? 2.1 ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for dsp56362. 4 all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 3 t c for read-after-read or write-after-write sequences). 5 brw[1:0] (dram control register bits) de fines the number of wait states that should be inserted in each dram out-of-page access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-12 dram page mode timings, four wait states 100 and 120mhz 1, 2, 3, 4 (continued) no. characteristics symbol expression 100 mhz 120 mhz unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-26 freescale semiconductor figure 3-14 dram page mode write accesses ras cas a0?a17 wr rd d0?d23 column row data out data out data out last column column add address address address 136 135 131 139 141 137 140 142 147 144 151 148 146 155 156 150 138 145 143 149 aa0473
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-27 figure 3-15 dram page mode read accesses ras cas a0?a17 wr rd d0?d23 column last column column row data in data in data in add address address address 136 135 131 137 140 141 142 143 152 133 153 132 138 139 134 154 aa0474
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-28 freescale semiconductor figure 3-16 dram out-of-page wait states selection guide table 3-13 dram out-of-page and re fresh timings, f our wait states 1, 2 no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max 157 random read or write cycle time t rc 5 t c 250.0 ? 166.7 ? ns 158 ras assertion to data valid (read) t rac 2.75 t c ? 7.5 ? 130.0 ? 84.2 ns 159 cas assertion to data valid (read) t cac 1.25 t c ? 7.5 ? 55.0 ? 34.2 ns 160 column address valid to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 162 ras deassertion to ras assertion t rp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 163 ras assertion pulse width t ras 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 164 cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns chip frequency (mhz) dram type (trac ns) 100 80 70 50 66 80 100 4 wait states 8 wait states 11 wait states 15 wait states note: this figure should be use for primary selection. for exact and detailed timings see the following tables. 60 40 120 aa0475
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-29 165 ras assertion to cas deassertion t csh 2.75 t c ? 4.0 133.5 ? 87.7 ? ns 166 cas assertion pulse width t cas 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 167 ras assertion to cas assertion t rcd 1.5 t c 2 73.0 77.0 48.0 52.0 ns 168 ras assertion to co lumn address valid t rad 1.25 t c 2 60.5 64.5 39.7 43.7 ns 169 cas deassertion to ras assertion t crp 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 170 cas deassertion pulse width t cp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 171 row address valid to ras assertion t asr 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 172 ras assertion to row address not valid t rah 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 173 column address valid to cas assertion t asc 0.25 t c ? 4.0 8.5 ? 4.3 ? ns 174 cas assertion to colu mn address not valid t cah 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 175 ras assertion to colu mn address not valid t ar 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 176 column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 177 wr deassertion to cas assertion t rcs 1.5 t c ? 3.8 71.2 ? 46.2 ? ns 178 cas deassertion to wr assertion t rch 0.75 t c ? 3.7 33.8 ? 21.3 ? ns 179 ras deassertion to wr assertion t rrh 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 180 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 70.8 ? 45.8 ? ns 181 ras assertion to wr deassertion t wcr 3 t c ? 4.2 145.8 ? 95.8 ? ns 182 wr assertion pulse width t wp 4.5 t c ? 4.5 220.5 ? 145.5 ? ns 183 wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 233.2 ? 154.0 ? ns 184 wr assertion to cas deassertion t cwl 4.25 t c ? 4.3 208.2 ? 137.4 ? ns 185 data valid to cas assertion (write) t ds 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 186 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 187 ras assertion to data not valid (write) t dhr 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 188 wr assertion to cas assertion t wcs 3 t c ? 4.3 145.7 ? 95.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.25 t c ? 4.0 58.5 ? 37.7 ? ns table 3-13 dram out-of-page and refresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-30 freescale semiconductor 191 rd assertion to ras deassertion t roh 4.5 t c ? 4.0 221.0 ? 146.0 ? ns 192 rd assertion to data valid t ga 4 t c ? 7.5 ? 192.5 ? 125.8 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 195 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns 1 the number of wait states for out of page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 reduced dsp clock speed allows use of dram ou t-of-page access with four wait states. see figure 3-16 . table 3-14 dram out-of-page and refresh timings, eight wait states 1, 2 no. characteristics 3 symbol expression 4 80 mhz unit min max 157 random read or write cycle time t rc 9 t c 112.5 ? ns 158 ras assertion to data valid (read) t rac 4.75 t c ? 6.5 52.9 ns 159 cas assertion to data valid (read) t cac 2.25 t c ? 6.5 ? 21.6 ns 160 column address valid to data valid (read) t aa 3 t c ? 6.5 ? 31.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 162 ras deassertion to ras assertion t rp 3.25 t c ? 4.0 36.6 ? ns 163 ras assertion pulse width t ras 5.75 t c ? 4.0 67.9 ? ns 164 cas assertion to ras deassertion t rsh 3.25 t c ? 4.0 36.6 ? ns 165 ras assertion to cas deassertion t csh 4.75 t c ? 4.0 55.4 ? ns 166 cas assertion pulse width t cas 2.25 t c ? 4.0 24.1 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 2 29.3 33.3 ns 168 ras assertion to column address valid t rad 1.75 t c 2 19.9 23.9 ns 169 cas deassertion to ras assertion t crp 4.25 t c ? 4.0 49.1 ? ns 170 cas deassertion pulse width t cp 2.75 t c ? 4.0 30.4 ? ns 171 row address valid to ras assertion t asr 3.25 t c ? 4.0 36.6 ? ns table 3-13 dram out-of-page and refresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-31 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 17.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 5.4 ? ns 174 cas assertion to column address not valid t cah 3.25 t c ? 4.0 36.6 ? ns 175 ras assertion to column address not valid t ar 5.75 t c ? 4.0 67.9 ? ns 176 column address valid to ras deassertion t ral 4 t c ? 4.0 46.0 ? ns 177 wr deassertion to cas assertion t rcs 2 t c ? 3.8 21.2 ? ns 178 cas deassertion to wr 5 assertion t rch 1.25 t c ? 3.7 11.9 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 3.0 0.1 ? ns 180 cas assertion to wr deassertion t wch 3 t c ? 4.2 33.3 ? ns 181 ras assertion to wr deassertion t wcr 5.5 t c ? 4.2 64.6 ? ns 182 wr assertion pulse width t wp 8.5 t c ? 4.5 101.8 ? ns 183 wr assertion to ras deassertion t rwl 8.75 t c ? 4.3 105.1 ? ns 184 wr assertion to cas deassertion t cwl 7.75 t c ? 4.3 92.6 ? ns 185 data valid to cas assertion (write) t ds 4.75 t c ? 4.0 55.4 ? ns 186 cas assertion to data not valid (write) t dh 3.25 t c ? 4.0 36.6 ? ns 187 ras assertion to data not valid (write) t dhr 5.75 t c ? 4.0 67.9 ? ns 188 wr assertion to cas assertion t wcs 5.5 t c ? 4.3 64.5 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 14.8 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.75 t c ? 4.0 17.9 ? ns 191 rd assertion to ras deassertion t roh 8.5 t c ? 4.0 102.3 ? ns 192 rd assertion to data valid t ga 7.5 t c ? 6.5 ? 87.3 ns 193 rd deassertion to data not valid 3 t gz 0.0 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 9.1 ? ns 195 wr deassertion to data high impedance 0.25 t c ?3.1ns 1 the number of wait states for out-of -page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 the asynchronous delays specified in the expressions are valid for dsp56362. 5 either t rch or t rrh must be satisf ied for read cycles. table 3-14 dram out-of-page and refresh timings, eight wait states 1, 2 (continued) no. characteristics 3 symbol expression 4 80 mhz unit min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-32 freescale semiconductor table 3-15 dram out-of-page and refresh timings, eleven wait states 1, 2 no. characteristics 3 symbol expression 4 100 mhz unit min max 157 random read or write cycle time t rc 12 t c 120.0 ? ns 158 ras assertion to data valid (read) t rac 6.25 t c ? 7.0 ? 55.5 ns 159 cas assertion to data valid (read) t cac 3.75 t c ? 7.0 ? 30.5 ns 160 column address valid to data valid (read) t aa 4.5 t c ? 7.0 ? 38.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 162 ras deassertion to ras assertion t rp 4.25 t c ? 4.0 38.5 ? ns 163 ras assertion pulse width t ras 7.75 t c ? 4.0 73.5 ? ns 164 cas assertion to ras deassertion t rsh 5.25 t c ? 4.0 48.5 ? ns 165 ras assertion to cas deassertion t csh 6.25 t c ? 4.0 58.5 ? ns 166 cas assertion pulse width t cas 3.75 t c ? 4.0 33.5 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 4.0 21.0 29.0 ns 168 ras assertion to column address valid t rad 1.75 t c 4.0 13.5 21.5 ns 169 cas deassertion to ras assertion t crp 5.75 t c ? 4.0 53.5 ? ns 170 cas deassertion pulse width t cp 4.25 t c ? 4.0 38.5 ? ns 171 row address valid to ras assertion t asr 4.25 t c ? 4.0 38.5 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 13.5 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? ns 174 cas assertion to column address not valid t cah 5.25 t c ? 4.0 48.5 ? ns 175 ras assertion to column address not valid t ar 7.75 t c ? 4.0 73.5 ? ns 176 column address valid to ras deassertion t ral 6 t c ? 4.0 56.0 ? ns 177 wr deassertion to cas assertion t rcs 3.0 t c ? 4.0 26.0 ? ns 178 cas deassertion to wr 5 assertion t rch 1.75 t c ? 4.0 13.5 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 3.0 ? ? ns 0.25 t c ? 2.0 0.5 ? 180 cas assertion to wr deassertion t wch 5 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 7.5 t c ? 4.2 70.8 ? ns
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-33 182 wr assertion pulse width t wp 11.5 t c ? 4.5 110.5 ? ns 183 wr assertion to ras deassertion t rwl 11.75 t c ? 4.3 113.2 ? ns 184 wr assertion to cas deassertion t cwl 10.25 t c ? 4.3 103.2 ? ns 185 data valid to cas assertion (write) t ds 5.75 t c ? 4.0 53.5 ? ns 186 cas assertion to data not valid (write) t dh 5.25 t c ? 4.0 48.5 ? ns 187 ras assertion to data not valid (write) t dhr 7.75 t c ? 4.0 73.5 ? ns 188 wr assertion to cas assertion t wcs 6.5 t c ? 4.3 60.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 2.75 t c ? 4.0 23.5 ? ns 191 rd assertion to ras deassertion t roh 11.5 t c ? 4.0 111.0 ? ns 192 rd assertion to data valid t ga 10 t c ? 7.0 93.0 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5ns 1 the number of wait states for out-o f-page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 the asynchronous delays specified in the expressions are valid for dsp56362. 5 either t rch or t rrh must be satisfied for read cycles. table 3-16 dram out-of-page and refresh ti mings, fifteen wait states 100 and 120mhz 1, 2 no. characteristics 3 symbol expression 100 mhz 120 mhz unit min max min max 157 random read or write cycle time t rc 16 t c 160.0 ? 133.3 ? ns 158 ras assertion to data valid (read) t rac 8.25 t c ? 5.7 ? 76.8 ? 63.0 ns 159 cas assertion to data valid (read) t cac 4.75 t c ? 5.7 ? 41.8 ? 33.9 ns 160 column address valid to data valid (read) t aa 5.5 t c ? 5.7 ? 49.3 40.1 ns table 3-15 dram out-of-page and refresh timings, eleven wait states 1, 2 (continued) no. characteristics 3 symbol expression 4 100 mhz unit min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-34 freescale semiconductor 161 cas deassertion to data not valid (read hold time) t off 0.0 0.0 ? 0.0 ? ns 162 ras deassertion to ras assertion t rp 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 163 ras assertion pulse width t ras 9.75 t c ? 4.0 93.5 ? 77.2 ? ns 164 cas assertion to ras deassertion t rsh 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 165 ras assertion to cas deassertion t csh 8.25 t c ? 4.0 78.5 ? 64.7 ? ns 166 cas assertion pulse width t cas 4.75 t c ? 4.0 43.5 ? 35.6 ? ns 167 ras assertion to cas assertion t rcd 3.5 t c 2 33.0 37.0 27.2 31.2 ns 168 ras assertion to column address valid t rad 2.75 t c 2 25.5 29.5 20.9 24.9 ns 169 cas deassertion to ras assertion t crp 7.75 t c ? 4.0 73.5 ? 60.6 ? ns 170 cas deassertion pulse width t cp 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 171 row address valid to ras assertion t asr 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 172 ras assertion to row address not valid t rah 2.75 t c ? 4.0 23.5 ? 18.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? 2.2 ? ns 174 cas assertion to column address not valid t cah 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 175 ras assertion to column address not valid t ar 9.75 t c ? 4.0 93.5 ? 77.2 ? ns 176 column address valid to ras deassertion t ral 7 t c ? 4.0 66.0 ? 54.3 ? ns 177 wr deassertion to cas assertion t rcs 5 t c ? 3.8 46.2 ? 37.9 ? ns 178 cas deassertion to wr 4 assertion t rch 1.75 t c ? 3.7 13.8 ? 10.9 ? ns 179 ras deassertion to wr 4 assertion t rrh 0.25 t c ? 2.0 0.5 ? 0.1 ? ns 180 cas assertion to wr deassertion t wch 6 t c ? 4.2 55.8 ? 45.8 ? ns 181 ras assertion to wr deassertion t wcr 9.5 t c ? 4.2 90.8 ? 75.0 ? ns 182 wr assertion pulse width t wp 15.5 t c ? 4.5 150.5 ? 124.7 ? ns 183 wr assertion to ras deassertion t rwl 15.75 t c ? 4.3 153.2 ? 126.9 ? ns 184 wr assertion to cas deassertion t cwl 14.25 t c ? 4.3 138.2 ? 114.4 ? ns 185 data valid to cas assertion (write) t ds 8.75 t c ? 4.0 83.5 ? 68.9 ? ns table 3-16 dram out-of-page and refresh timings, fifteen wait states 100 and 120mhz 1, 2 (continued) no. characteristics 3 symbol expression 100 mhz 120 mhz unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-35 186 cas assertion to data not valid (write) t dh 6.25 t c ? 4.0 58.5 ? 48.1 ? ns 187 ras assertion to data not valid (write) t dhr 9.75 t c ? 4.0 93.5 ? 77.2 ? ns 188 wr assertion to cas assertion t wcs 9.5 t c ? 4.3 90.7 ? 74.9 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? 8.5 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 4.75 t c ? 4.0 43.5 ? 35.6 ? ns 191 rd assertion to ras deassertion t roh 15.5 t c ? 4.0 151.0 ? 125.2 ? ns 192 rd assertion to data valid t ga 14 t c ? 5.7 ? 134.3 ? 111.0 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 7.2 ? 5.9 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5?2.1ns 1 the number of wait states for out-of-page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 either t rch or t rrh must be satisfied for read cycles. table 3-16 dram out-of-page and refresh timings, fifteen wait states 100 and 120mhz 1, 2 (continued) no. characteristics 3 symbol expression 100 mhz 120 mhz unit min max min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-36 freescale semiconductor figure 3-17 dram out-of-page read access ras cas a0?a17 wr rd d0?d23 data row address column address in 157 163 165 162 162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 aa0476
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-37 figure 3-18 dram out-of-page write access ras cas a0?a17 wr rd d0?d23 data out column address row address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180 188 182 184 183 187 185 194 186 195 aa0477
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-38 freescale semiconductor figure 3-19 dram refresh access 3.10.3 synchronous timings (sram) table 3-17 external bus synchronous timings (sram access) 1 no. characteristics expression 2 , 3 100 mhz unit min max 198 clkout high to address, and aa valid 4 0.25 t c + 4.0 ? 6.5 ns 199 clkout high to address, and aa invalid 4 0.25 t c 2.5 ? ns 200 ta valid to clkout high (setup time) 4.0 ? ns 201 clkout high to ta invalid (hold time) 0.0 ? ns 202 clkout high to data out active 0.25 t c 2.5 ? ns 203 clkout high to data out valid 0.25 t c + 4.0 3.3 6.5 ns 204 clkout high to data out invalid 0.25 t c 2.5 ? ns 205 clkout high to data out high impedance 0.25 t c ?2.5ns 206 data in valid to clkout high (setup) 4.0 ? ns 207 clkout high to data in invalid (hold) 0.0 ? ns 208 clkout high to rd assertion 0.75 t c + 4.0 8.2 11.5 ns ras cas wr 157 163 162 162 190 170 165 189 177 aa0478
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-39 209 clkout high to rd deassertion 0.0 4.0 ns 210 clkout high to wr assertion 5 0.5 t c + 4.3 [ws = 1 or ws 4] 6.3 9.3 ns all frequencies: [2 ws 3] 1.3 4.3 211 clkout high to wr deassertion 0.0 3.8 ns 1 external bus synchronous timings should be used only for reference to the clock and not for relative timings. 2 ws is the number of wait states specified in the bcr. 3 the asynchronous delays specified in the expressions are valid for dsp56362. 4 t198 and t199 are valid for address trace mode if the ate bit in the omr is set. use the status of br (see t212) to determine whether the access referenced by a0?a23 is internal or external, when this mode is enabled 5 if ws > 1, wr assertion refers to the next rising edge of clkout. table 3-17 external bus synchronous timings (sram access) 1 (continued) no. characteristics expression 2 , 3 100 mhz unit min max
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-40 freescale semiconductor figure 3-20 synchronous bus timings sram 1 ws (bcr controlled) wr rd data out d0?d23 clkout ta data in d0?d23 a0?a17 aa0?aa3 199 201 200 211 210 208 209 207 198 205 204 203 202 206 aa0479
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-41 figure 3-21 synchronous bus timings sram 2 ws (ta controlled) 3.10.4 arbitration timings table 3-18 arbitration bus timings 1 no. characteristics expression 100 mhz unit min max 212 clkout high to br assertion/deassertion 2 1.0 4.0 ns 213 bg asserted/deasserted to clkout high (setup) 4.0 ? ns 214 clkout high to bg deasserted/asserted (hold) 0.0 ? ns 215 bb deassertion to clkout high (input setup) 4.0 ? ns 216 clkout high to bb assertion (input hold) 0.0 ? ns 217 clkout high to bb assertion (output) 1.0 4.0 ns a0?a17 wr rd data out d0?d23 aa0?aa3 clkout ta data in d0?d23 198 199 201 200 201 211 209 207 208 210 200 203 202 205 204 206 aa0480
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-42 freescale semiconductor figure 3-22 bus acquisition timings 218 clkout high to bb deassertion (output) 1.0 4.0 ns 219 bb high to bb high impedance (output) ? 4.5 ns 220 clkout high to address and controls active 0.25 t c 2.5 ? ns 221 clkout high to address and controls high impedance 0.25 t c ?2.5ns 222 clkout high to aa active 0.25 t c 2.5 ? ns 223 clkout high to aa deassertion 0.25 t c + 4.0 3.2 6.5 ns 224 clkout high to aa high impedance 0.75 t c ?7.5ns 1 the asynchronous delays specified in the expressions are valid for dsp56362. 2 t212 is valid for address trace mode when the ate bit in the omr is set. br is deasserted for internal accesses and asserted for external accesses. table 3-18 arbitration bus timings 1 (continued) no. characteristics expression 100 mhz unit min max a0?a17 bb aa0?aa3 clkout br bg rd, wr 212 214 216 215 220 217 213 222 aa0481
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-43 figure 3-23 bus release timings case 1 (brt bit in omr cleared) a0?a17 bb aa0?aa3 clkout br bg rd, wr 212 214 218 221 224 223 213 219 aa0482
external memory expansion port (port a) dsp56362 technical data, rev. 4 3-44 freescale semiconductor figure 3-24 bus release timings case 2 (brt bit in omr set) table 3-19 asynchronous bus arbitration timing no. characteristics expression 100 mhz unit min max 250 bb assertion window from bg input negation. 2 .5* tc + 5 ? 20 ns 251 delay from bb assertion to bg assertion 2 * tc + 5 20 ? ns notes: 1. bit 13 in the omr register must be se t to enter asynchronous arbitration mode 2. at 100 mhz it is recommended to use asynchronous arbitration mode. 3. if asynchronous arbitration mode is active, none of the timings in table 3-19 is required. 4. in order to guarantee timings 250, and 251, it is recomme nded to assert bg inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in figure 3-25 . a0?a17 bb aa0?aa3 clkout br bg rd, wr 223 218 219 214 212 213 221 224 aa0483
external memory expansion port (port a) dsp56362 technical data, rev. 4 freescale semiconductor 3-45 figure 3-25 asynchronous bus arbitration timing figure 3-26 asynchronous bus arbitration timing background explanation for as ynchronous bus arbitration: the asynchronous bus arbitration is enabled by internal synchronization circuits on bg , and bb inputs. these synchronization circuits add delay from the external signal until it is exposed to internal logic. as a result of this delay, a 56300 part may as sume mastership and assert bb , for some time after bg is negated. this is the reason for timing 250. once bb is asserted, there is a synchronization delay from bb assertion to the time this assertion is exposed to other 56300 componen ts which are poten tial masters on the same bus. if bg input is asserted before that time, a situation of bg asserted, and bb negated, may cause another 56300 component to assume mastership at the same time. ther efore some non-overlap period between one bg input active to another bg input active, is required. timing 251 ensures that such a situation is avoided. bg1 bb 250 251 bg2 bg1 bg2 250+251
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 3-46 freescale semiconductor 3.11 parallel host interface (hdi08) timing table 3-20 host interface (hdi08) timing 1, 2 no. characteristics 3 expression 100 mhz unit min max 317 read data strobe assertion width 4 hack read assertion width t c + 9.9 19.9 ? ns 318 read data strobe deassertion width 4 hack read deassertion width ?9.9?ns 319 read data strobe deassertion width 4 after ?last data register? reads 5 , 6 , or between two consecutive cvr, icr, or isr reads 7 hack deassertion width after ?last data register? reads 5, 6 2.5 t c + 6.6 31.6 ? ns 320 write data strobe assertion width 8 hack write assertion width ? 13.2 ? ns 321 write data strobe deassertion width 8 hack write deassertion width after icr, cvr and ?last data register? writes 5 2.5 t c + 6.6 31.6 ? ns after ivr writes, or after txh:txm writes (with hbe=0), or after txl:txm writes (with hbe=1) 16.5 ? 322 has assertion width ? 9.9 ? ns 323 has deassertion to data strobe assertion 9 ?0.0?ns 324 host data input setup time before write data strobe deassertion 8 host data input setup time before hack write deassertion ?9.9?ns 325 host data input hold time after write data strobe deassertion 8 host data input hold time after hack write deassertion ?3.3?ns 326 read data strobe assertion to output data active from high impedance 4 hack read assertion to output data active from high impedance ?3.3?ns 327 read data strobe assertion to output data valid 4 hack read assertion to output data valid ??24.2ns 328 read data strobe deassertion to output data high impedance 4 hack read deassertion to output data high impedance ??9.9ns 329 output data hold time after read data strobe deassertion 4 output data hold time after hack read deassertion ?3.3?ns 330 hcs assertion to read data strobe deassertion 4 t c +9.9 19.9 ? ns 331 hcs assertion to write data strobe deassertion 8 ?9.9?ns 332 hcs assertion to output data valid ? ? 19.1 ns
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 freescale semiconductor 3-47 333 hcs hold time after data strobe deassertion 9 ?0.0?ns 334 address (ad7?ad0) setup time before has deassertion (hmux=1) ?4.7?ns 335 address (ad7?ad0) hold time after has deassertion (hmux=1) ? 3.3 ? ns 336 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w setup time before data strobe assertion 9 read write ? 0 4.7 ? ? ns 337 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w hold time after data strobe deassertion 9 ?3.3?ns 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 4, 5, 10 t c 10 ? ns 339 delay from write data strobe deassertion to host request assertion for ?last data register? write 5, 8, 10 2 t c 20 ? ns 340 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod = 0) 5, 9, 10 ??19.1ns 341 delay from data strobe assertion to host request deassertion for ?last data register? read or wr ite (hrod = 1, open drain host request) 5, 9, 10, 11 ? ? 300.0 ns 342 delay from dma hack deassertion to horeq assertion for ?last data register? read 5 for ?last data register? write 5 for other cases 2 t c + 19.1 1.5 t c + 19.1 39.1 34.1 0.0 ? ? ? ns 343 delay from dma hack assertion to horeq deassertion hrod = 0 5 ? ?20.2 ns 344 delay from dma hack assertion to horeq deassertion for ?last data register? read or write hrod = 1, open drain host request 5, 11 ? ? 300.0 ns 1 see host port usage considerations in the dsp56362 user design manual. 2 in the timing diagrams below, the controls pins are drawn as active low. the pin polarity is programmable. 3 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf 4 the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 5 the ?last data register? is the register at address $7, which is the last location to be read or written in data transfers. thi s is rxl/txl in the little endian mode (hbe = 0), or rxh/txh in the big endian mode (hbe = 1). 6 this timing is applicable only if a read from the ?last data regi ster? is followed by a read from the rxl, rxm, or rxh register s without first polling rxdf or hreq bits, or waiting for the assertion of the horeq signal. 7 this timing is applicable only if two consecutiv e reads from one of these registers are executed. table 3-20 host interface (hdi08) timing 1, 2 (continued) no. characteristics 3 expression 100 mhz unit min max
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 3-48 freescale semiconductor figure 3-27 host interrupt vector register (ivr) read timing diagram figure 3-28 read timing diagram, non-multiplexed bus 8 the write data strobe is hwr in the dual data stro be mode and hds in the single data strobe mode. 9 the data strobe is host read (hrd) or host write (hwr) in the dual data strobe mode and host data strobe (hds) in the single data strobe mode. 10 the host request is horeq in the single host request mode and hrrq and htrq in the double host request mode. 11 in this calculation, the host request signal is pulled up by a 4.7 k ? resistor in the open-drain mode. hack hd7?hd0 horeq 329 317 318 328 326 327 aa1105 hrd, hds ha0?ha2 hcs hd0?hd7 horeq, 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 aa0484 hrrq, htrq
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 freescale semiconductor 3-49 figure 3-29 write timing diagram, non-multiplexed bus hwr, hds ha0?ha2 hcs hd0?hd7 horeq, hrrq, htrq 336 331 337 321 320 324 325 339 340 341 333 aa0485
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 3-50 freescale semiconductor figure 3-30 read timing di agram, multiplexed bus hrd, hds ha8?ha10 has had0?had7 horeq, hrrq, htrq address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 aa0486 322
parallel host interface (hdi08) timing dsp56362 technical data, rev. 4 freescale semiconductor 3-51 figure 3-31 write timing diagram, multiplexed bus figure 3-32 host dma write timing diagram hwr, hds ha8?ha10 horeq, hrrq, htrq has had0?had7 address data 320 321 325 324 335 341 339 336 334 340 322 323 aa0487 horeq (output) hack (input) h0?h7 (input) data valid txh/m/l write 320 321 343 342 324 344 325
serial host interface spi protocol timing dsp56362 technical data, rev. 4 3-52 freescale semiconductor figure 3-33 host dma read timing diagram 3.12 serial host interface spi protocol timing table 3-21 serial host interface spi protocol timing no. characteristics mode filter mode expression 100mhz unit min max 140 tolerable spike width on clock or data in ? bypassed narrow wide ?? ? ? 0 50 100 ns 141 minimum serial clock cycle = t spicc (min) master bypassed narrow wide 6 t c +46 6 t c +152 6 t c +223 106 212 283 ? ? ? ns 142 serial clock high period master bypassed narrow wide 0.5 t spicc ?10 0.5 t spicc ?10 0.5 t spicc ?10 43 96 131 ? ? ? ns slave bypassed narrow wide 2.5 t c +12 2.5 t c +102 2.5 t c +189 37 127 214 ? ? ? 143 serial clock low period master bypassed narrow wide 0.5 t spicc ?10 0.5 t spicc ?10 0.5 t spicc ?10 43 96 131 ? ? ? ns slave bypassed narrow wide 2.5 t c +12 2.5 t c +102 2.5 t c +189 37 127 214 ? ? ? 326 317 318 327 328 329 data valid horeq (output) hack (input) h0-h7 (output) rxh read 343 342 342
serial host interface spi protocol timing dsp56362 technical data, rev. 4 freescale semiconductor 3-53 144 serial clock rise/fall time master ? ? ? 10 ns slave ? ? ? 2000 146 ss assertion to first sck edge cpha = 0 slave bypassed narrow wide 3.5 t c +15 0 0 50 0 0 ? ? ? ns cpha = 1 slave bypassed narrow wide 10 0 0 10 0 0 ? ? ? 147 last sck edge to ss not asserted slave bypassed narrow wide 12 102 189 12 102 189 ? ? ? ns 148 data input valid to sck edge (data input set-up time) master/ slave bypassed narrow wide 0 max{(20-t c ), 0} max{(40-t c ), 0} 0 10 30 ? ? ? ns 149 sck last sampling edge to data input not valid master/ slave bypassed narrow wide 2.5 t c +10 2.5 t c +30 2.5 t c +50 35 55 75 ? ? ? ns 150 ss assertion to data out active slave ? 2 2 ? ns 151 ss deassertion to data high impedance slave ? 9 ? 9 ns 152 sck edge to data out valid (data out delay time) master/ slave bypassed narrow wide 2 t c +33 2 t c +123 2 t c +210 ? ? ? 53 143 230 ns 153 sck edge to data out not valid (data out hold time) master/ slave bypassed narrow wide t c +5 t c +55 t c +106 15 65 116 ? ? ? ns 154 ss assertion to data out valid (cpha = 0) slave ? t c +33 ? 43 ns 157 first sck sampling edge to hreq output deassertion slave bypassed narrow wide 2.5 t c +30 2.5 t c +120 2.5 t c +217 ? ? ? 55 145 242 ns 158 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed narrow wide 2.5 t c +30 2.5 t c +80 2.5 t c +136 55 105 161 ? ? ? ns table 3-21 serial host interface spi protocol timing (continued) no. characteristics mode filter mode expression 100mhz unit min max
serial host interface spi protocol timing dsp56362 technical data, rev. 4 3-54 freescale semiconductor figure 3-34 spi mast er timing (cpha = 0) 159 ss deassertion to hreq output not deasserted (cpha = 0) slave ? 2.5 t c +30 55 ? ns 160 ss deassertion pulse width (cpha = 0) slave ? t c +6 16 ? ns 161 hreq in assertion to first sck edge master bypassed narrow wide 0.5 t spicc + 2.5 t c +43 0.5 t spicc + 2.5 t c +43 0.5 t spicc + 2.5 t c +43 121 174 209 ? ? ? ns 162 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? 0 0 ? ns 163 first sck edge to hreq in not asserted (hreq in hold time) master ? 0 0 ? ns note: periodically sampled, not 100% tested table 3-21 serial host interface spi protocol timing (continued) no. characteristics mode filter mode expression 100mhz unit min max ss (input) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 aa0271 sck (cpol=0 (output) sck (cpol = 1 (output)
serial host interface spi protocol timing dsp56362 technical data, rev. 4 freescale semiconductor 3-55 figure 3-35 spi slave timing (cpha = 0) ss (input) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 aa0272 sck (cpol = 0 (output) sck (cpol = 1 (output)
serial host interface spi protocol timing dsp56362 technical data, rev. 4 3-56 freescale semiconductor figure 3-36 spi mast er timing (cpha = 1) ss (input) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 aa0272 sck (cpol = 0 (output) sck (cpol = 1 (output)
serial host interface spi protocol timing dsp56362 technical data, rev. 4 freescale semiconductor 3-57 figure 3-37 spi slave timing (cpha = 0) ss (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 153 151 valid valid 148 149 147 160 146 aa0273 sck (cpol = 0) (input) sck (cpol = 1) (input)
serial host interface spi protocol timing dsp56362 technical data, rev. 4 3-58 freescale semiconductor figure 3-38 spi slave timing (cpha = 1) ss (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 valid valid 148 147 146 152 149 157 aa0274 sck (cpol = 0) (input) sck (cpol = 1) (input)
serial host interface (shi) i 2 c protocol timing dsp56362 technical data, rev. 4 freescale semiconductor 3-59 3.13 serial host interface (shi) i 2 c protocol timing table 3-22 shi i 2 c protocol timing standard i 2 c* no. characteristics symbol/ expression standard fast-mode unit min max min max tolerable spike width on scl or sda filters bypassed narrow filters enabled wide filters enabled ? ? ? ? 0 50 100 ? ? ? 0 50 100 ns 171 scl clock frequency f scl ? 100 ? 400 khz 172 bus free time t buf 4.7 ? 1.3 ? s 173 start condition set-up time t su;sta 4.7 ? 0.6 ? s 174 start condition hold time t hd;sta 4.0 ? 0.6 ? s 175 scl low period t low 4.7 ? 1.3 ? s 176 scl high period t high 4.0 ? 1.3 ? s 177 scl and sda rise time t r ? 1000 20 + 0.1 c b 300 ns 178 scl and sda fall time t f ? 300 20 + 0.1 c b 300 ns 179 data set-up time t su;dat 250 ? 100 ? ns 180 data hold time t hd;dat 0.0 ? 0.0 0.9 s 181 stop condition set-up time t su;sto 4.0 ? 0.6 ? s 182 capacitive load for each line c b ? 400 ? 400 pf 183 dsp clock frequency filters bypassed narrow filters enabled wide filters enabled f dsp 10.6 11.8 13.1 ? ? ? 28.5 39.7 61.0 ? ? ? mhz 184 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns 186 first scl sampling edge to hreq output deassertion filters bypassed narrow filters enabled wide filters enabled t ng;rqo 2 t c + 30 2 t c + 120 2 t c + 208 ? ? ? 50 140 228 ? ? ? 50 140 228 ns
serial host interface (shi) i 2 c protocol timing dsp56362 technical data, rev. 4 3-60 freescale semiconductor 3.13.1 programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm[5:0] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is where: hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide -by-eight prescaler is operational. when hrs is set, the prescaler is bypassed. hdm[7:0] are the divider modulus select bits. a divide ratio from 1 to 64 (hdm[5:0] = 0 to $3f) may be selected. in i 2 c mode, the user may select a value fo r the programmed seri al clock cycle from to the programmed serial clock cycle (t i2ccp ), scl rise time (t r ), and the filters selected should be chosen in order to achieve the desired scl frequency, as shown in table 3-23 187 last scl edge to hreq output not deasserted filters bypassed narrow filters enabled wide filters enabled t as;rqo 2 t c + 30 2 t c + 80 2 t c + 135 50 100 155 ? ? ? 50 100 155 ? ? ? ns 188 hreq in assertion to first scl edge filters bypassed narrow filters enabled wide filters enabled t as;rqi 0.5 t i 2 ccp ? 0.5 t c - 21 4327 4282 4238 ? ? ? 927 882 838 ? ? ? ns note: r p (min) = 1.5 k? table 3-22 shi i 2 c protocol timing (continued) standard i 2 c* no. characteristics symbol/ expression standard fast-mode unit min max min max t i 2 ccp t c 2 hdm 7 0 : [] 1 + () 71 ( hrs ) 1 + ? () [] = 6t c if hdm 5 0 : [] 02 and hrs $ 1 == () 4096 t c if hdm 7 0 : [] ff and hrs $ 0 == ()
serial host interface (shi) i 2 c protocol timing dsp56362 technical data, rev. 4 freescale semiconductor 3-61 . example: for dsp clock frequency of 100 mhz (i.e. t c = 10ns), operating in a standard-mode i 2 c environment (f scl = 100 khz (i.e. t scl = 10 s), t r = 1000ns), with filters bypassed choosing hrs = 0 gives thus the hdm[7:0] value shoul d be programmed to $38 (=56). figure 3-39 i 2 c timing table 3-23 scl serial clock cycle generated as master filters bypassed t i 2 ccp + 2.5 t c + 45ns + t r narrow filters enabled t i 2 ccp + 2.5 t c + 135ns + t r wide filters enabled t i 2 ccp + 2.5 t c + 223ns + t r t i 2 ccp 10 s 2.5 10ns 45ns 1000ns ? ? ? 8930ns == hdm 7 0 : [] 8930ns 2 ( 10ns 8 ) 1 55.8 = ? ? = start scl hreq sda ack msb lsb stop 171 stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 aa0275
enhanced serial audio interface timing dsp56362 technical data, rev. 4 3-62 freescale semiconductor 3.14 enhanced serial audio interface timing table 3-24 enhanced serial audio interface timing no. characteristics 1 , 2, 3 symbol expression 100 mhz condition 4 unit min max 430 clock cycle 5 t ssicc 4 x t c rxc:3 xt c txc: max [3xt c ;t 454 ] 40.0 30 40 ? ? i ck x ck x ck ns 431 clock high period for internal clock for external clock ? 2 t c ? 10.0 1.5 t c 10.0 15.0 ? ? ns 432 clock low period for internal clock for external clock ? 2 t c ? 10.0 1.5 t c 10.0 15.0 ? ? ns 433 rxc rising edge to fsr out (bl) high ? ? ? 37.0 x ck ns ?22.0 i ck a 434 rxc rising edge to fsr out (bl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 435 rxc rising edge to fsr out (wr) high 6 ??? ? 39.0 24.0 x ck i ck a ns 436 rxc rising edge to fsr out (wr) low 6 ?? ? 39.0 24.0 x ck i ck a ns 437 rxc rising edge to fsr out (wl) high ? ? ? ? 36.0 21.0 x ck i ck a ns 438 rxc rising edge to fsr out (wl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 439 data in setup time before rxc (txc in synchronous mode) falling edge ??0.0 19.0 ? ? x ck i ck ns 440 data in hold time after rxc falling edge ? ? 5.0 3.0 ? ? x ck i ck ns 441 fsr input (bl, wr) high before rxc falling edge 6 ??23.0 1.0 ? ? x ck i ck a ns 442 fsr input (wl) high before rxc falling edge ? ? 1.0 23.0 ? ? x ck i ck a ns
enhanced serial audio interface timing dsp56362 technical data, rev. 4 freescale semiconductor 3-63 443 fsr input hold time after rxc falling edge ? ? 3.0 0.0 ? ? x ck i ck a ns 444 flags input setup before rxc falling edge ? ? 0.0 19.0 ? ? x ck i ck s ns 445 flags input hold time after rxc falling edge ? ? 6.0 0.0 ? ? x ck i ck s ns 446 txc rising edge to fst out (bl) high ? ? ? ? 29.0 15.0 x ck i ck ns 447 txc rising edge to fst out (bl) low ? ? ? ? 31.0 17.0 x ck i ck ns 448 txc rising edge to fst out (wr) high 6 ??? ? 31.0 17.0 x ck i ck ns 449 txc rising edge to fst out (wr) low 6 ??? ? 33.0 19.0 x ck i ck ns 450 txc rising edge to fst out (wl) high ? ? ? ? 30.0 16.0 x ck i ck ns 451 txc rising edge to fst out (wl) low ? ? ? ? 31.0 17.0 x ck i ck ns 452 txc rising edge to data out enable from high impedance ??? ? 31.0 17.0 x ck i ck ns 453 txc rising edge to transmitter drive enable assertion ??? ? 34.0 20.0 x ck i ck ns 454 txc rising edge to data out valid ? 23 + 0.5 t c 21.0 ? ? 28.0 21.0 x ck i ck ns 455 txc rising edge to data out high impedance 7 ??? ? 31.0 16.0 x ck i ck ns 456 txc rising edge to transmitter drive enable deassertion 7 ??? ? 34.0 20.0 x ck i ck ns 457 fst input (bl, wr) setup time before txc falling edge 6 ??2.0 21.0 ? ? x ck i ck ns table 3-24 enhanced serial audio interface timing (continued) no. characteristics 1 , 2, 3 symbol expression 100 mhz condition 4 unit min max
enhanced serial audio interface timing dsp56362 technical data, rev. 4 3-64 freescale semiconductor 458 fst input (wl) to data out enable from high impedance ? ? ? 27.0 ? ns 459 fst input (wl) to transmitter drive enable assertion ? ? ? 31.0 ? ns 460 fst input (wl) setup time before txc falling edge ??2.0 21.0 ? ? x ck i ck ns 461 fst input hold time after txc falling edge ? ? 4.0 0.0 ? ? x ck i ck ns 462 flag output valid after txc rising edge ? ? ? ? 32.0 18.0 x ck i ck ns 463 hckr/hckt clock cycle ? ? 40.0 ? ns 464 hckt input rising edge to txc output ? ? ? 27.5 ns 465 hckr input rising edge to rxc output ? ? ? 27.5 ns 1 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 txc(sckt pin) = transmit clock rxc(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5 for the internal clock, the clock cycle at the pi n is defined by icyc and the esai control registers. 6 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7 periodically sampled and not 100% tested. table 3-24 enhanced serial audio interface timing (continued) no. characteristics 1 , 2, 3 symbol expression 100 mhz condition 4 unit min max
enhanced serial audio interface timing dsp56362 technical data, rev. 4 freescale semiconductor 3-65 figure 3-40 esai transmitter timing last bit see note txc (input/output) fst (bit) out fst (word) out data out transmitter drive enable fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can o ccur at the start of each time slot within the frame. in normal mode, the output flag st ate is asserted for the entire frame period. first bit 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 aa0490
enhanced serial audio interface timing dsp56362 technical data, rev. 4 3-66 freescale semiconductor figure 3-41 esai receiver timing figure 3-42 esai hckt timing rxc (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in last bit first bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 aa0491 hckt sckt(output) 464 463
digital audio transmitter timing dsp56362 technical data, rev. 4 freescale semiconductor 3-67 figure 3-43 esai hckr timing 3.15 digital audio transmitter timing figure 3-44 digital audio transmitter timing table 3-25 digital audio transmitter timing no. characteristic expression 100 mhz unit min max aci frequency 1 1 in order to assure proper operation of the dax, the aci frequency should be less than 1/2 of the dsp56362 internal clock frequency. for example, if the dsp56362 is running at 100 mhz internally, the aci frequency should be less than 50 mhz. ??50mhz 220 aci period 2 t c 20 ? ns 221 aci high duration 0.5 t c 5?ns 222 aci low duration 0.5 t c 5?ns 223 aci rising edge to ado valid 1.5 t c ?15ns hckr sckr (output) 465 463 aci ado 220 223 aa1280 221 222
timer timing dsp56362 technical data, rev. 4 3-68 freescale semiconductor 3.16 timer timing figure 3-45 tio timer event input restrictions figure 3-46 timer interrupt generation table 3-26 timer timing 1 1 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf no. characteristics expression 100 mhz unit min max 480 tio low 2 t c + 2.0 22.0 ? ns 481 tio high 2 t c + 2.0 22.0 ? ns 482 timer setup time from tio (input) assertion to clkout rising edge 9.0 10.0 ns 483 synchronous timer delay time from clkout rising edge to the external memory access address out valid caused by first interrupt instruction execution 10.25 t c + 1.0 103.5 ? ns 484 clkout rising edge to tio (output) assertion minimum maximum 0.5 t c + 3.5 0.5 t c + 19.8 8.5 ? ? 24.8 ns 485 clkout rising edge to tio (output) deassertion minimum maximum 0.5 t c + 3.5 0.5 t c + 19.0 8.5 ? ? 24.8 ns tio 481 480 aa0492 clkout tio (input) first interrupt instruction execution address 482 483 aa0493
gpio timing dsp56362 technical data, rev. 4 freescale semiconductor 3-69 figure 3-47 external pulse generation 3.17 gpio timing table 3-27 gpio timing 1 1 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf no. characteristics expression 100 mhz unit min max 490 clkout edge to gpio out valid (gpio out delay time) ?31.0ns 491 clkout edge to gpio out not valid (gpio out hold time) 3.0 ? ns 492 gpio in valid to clkout edge (gpio in set-up time) 12.0 ? ns 493 clkout edge to gpio in not valid (gpio in hold time) 0.0 ? ns 494 fetch to clkout edge before gpio change 6.75 t c 67.5 ? ns 495 gpio out rise time ? ? 13 ns 496 gpio out fall time ? ? 13 ns clkout tio (output) 484 485 aa0494
jtag timing dsp56362 technical data, rev. 4 3-70 freescale semiconductor figure 3-48 gpio timing 3.18 jtag timing table 3-28 jtag timing 1, 2 no. characteristics all frequencies unit min max 500 tck frequency of operation (1/(t c 3); maximum 22 mhz) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ? ns 502 tck clock pulse width measured at 1.5 v 20.0 ? ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ? ns 505 boundary scan input data hold time 24.0 ? ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 0.0 40.0 ns valid gpio (input) gpio (output) clkout (output) fetch the instruction move x0,x:(r0); x0 contains the new value of gpio and r0 contains the addre ss of gpio data register. a0?a17 490 491 492 494 493 aa0495 gpio (output) 495 496
jtag timing dsp56362 technical data, rev. 4 freescale semiconductor 3-71 figure 3-49 test clock input timing diagram 508 tms, tdi data setup time 5.0 ? ns 509 tms, tdi data hold time 25.0 ? ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 0.0 44.0 ns 512 trst assert time 100.0 ? ns 513 trst setup time to tck low 40.0 ? ns 1 v cc = 3.3 v 0.16v; t j = 0c to +100c, c l = 50 pf 2 all timings apply to once module data transfers be cause it uses the jtag port as an interface. table 3-28 jtag timing 1, 2 (continued) no. characteristics all frequencies unit min max tck (input) v m v m v ih v il 501 502 502 503 503 aa0496
jtag timing dsp56362 technical data, rev. 4 3-72 freescale semiconductor figure 3-50 boundary scan (jtag) timing diagram figure 3-51 test access port timing diagram tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid 505 504 506 507 506 aa0497 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms 508 509 510 511 510 aa0498
once module timing dsp56362 technical data, rev. 4 freescale semiconductor 3-73 figure 3-52 trst timing diagram 3.19 o n ce module timing figure 3-53 once?debug request table 3-29 once module timing 1 1 v cc = 3.3 v 0.16 v; t j = 0c to +100c, c l = 50 pf no. characteristics expression 100 mhz unit min max 500 tck frequency of operation 1/(t c 3), max 22.0 mhz 0.0 22.0 mhz 514 de assertion time in order to enter debug mode 1.5 t c + 10.0 25.0 ? ns 515 response time when dsp56362 is executing nop instructions from internal memory 5.5 t c + 30.0 ? 85.0 ns 516 debug acknowledge assertion time 3 t c + 10.0 40.0 ? ns tck (input) trst (input) 513 512 aa0499 de 516 515 514 aa0500
once module timing dsp56362 technical data, rev. 4 3-74 freescale semiconductor notes
dsp56362 technical data, rev. 4 freescale semiconductor 4-1 4 packaging 4.1 pin-out and package information this section provides information a bout the available package for this product, including diagrams of the package pinouts and tables describi ng how the signals described in section 2, ?signal/connection descriptions ? are allocated for the package. the dsp 56362 is available in a 144-pin lqfp package. 4.2 lqfp package description top view of the lqfp package is shown in figure 4-1 with its pin-outs. the lqfp package mechanical drawing is shown in figure 4-2 .
lqfp package description dsp56362 technical data, rev. 4 4-2 freescale semiconductor figure 4-1 dsp56362 thin quad flat pack (lqfp), top view sck ss hreq sdo0 sdo1 sdo2 sdo3 v ccs gnd s sdo4 sdo5 fst fsr sckt sckr hckt hckr v ccql gnd q v ccqh hds hrw hack horeq v ccs gnd s ado aci tio0 hcs ha9 ha8 has had7 had6 had5 had4 v cch gnd h had3 had2 had1 had0 reset v ccp pcap gnd p gnd p1 v ccqh aa3 aa2 cas de gnd q extal v ccql v ccc gnd c clkout pinit ta br bb v ccc gnd c wr rd aa1 aa0 bg a0 d7 d8 v ccd gnd d d9 d10 d11 d12 d13 d14 v ccd gnd d d15 d16 d17 d18 d19 v ccql gnd q d20 v ccd gnd d d21 d22 d23 trst tdo tdi tck tms mosi miso 1 37 73 109 (top view) orientation mark a1 v cca gnd a a2 a3 a4 a5 v cca gnd a a6 a7 a8 a9 v cca gnd a a10 a11 gnd q v ccql a12 a13 a14 v ccqh gnd a a15 a16 a17 d0 d1 d2 v ccd gnd d d3 d4 d5 d6 aa0301 modd modc modb moda note: because of size constraints in this figure, onl y one name is shown for multiplexed pins. refer to table 4-1 and table 4-2 for detailed information about pin functions and signal names. nc dsp56362
lqfp package description dsp56362 technical data, rev. 4 freescale semiconductor 4-3 table 4-1 dsp56362 lqfp signal identification by pin number pin no. signal name 1 pin no. signal name 1 pin no. signal name 1 1 sck/scl 26 gnd s 51 aa2/ras2 2ss /ha2 27 ado or pd1 52 cas 3 hreq 28 aci or pd0 53 de 4 sdo0 or pc11 29 tio0 54 gnd q 5sdo1 or pc10 30 hcs /hcs, ha10, or pb13 55 extal 6 sdo2/sdi3 or pc9 31 ha2, ha9, or pb10 56 v ccql 7 sdo3/sdi2 or pc8 32 ha1, ha8, or pb9 57 v ccc 8v ccs 33 ha0, has /has, or pb8 58 gnd c 9gnd s 34 h7, had7, or pb7 59 clkout 10 sdo4/sdi1 or pc7 35 h6, had6, or pb6 60 nc (not connected) 11 sdo5/sdi0 or pc6 36 h5, had5, or pb5 61 pinit /nmi 12 fst or pc4 37 h4, had4, or pb4 62 ta 13 fsr or pc1 38 v cch 63 br 14 sckt or pc3 39 gnd h 64 bb 15 sckr or pc0 40 h3, had3, or pb3 65 v ccc 16 hckt or pc5 41 h2, had2, or pb2 66 gnd c 17 hckr or pc2 42 h1, had1, or pb1 67 wr 18 v ccql 43 h0, had0, or pb0 68 rd 19 gnd q 44 reset 69 aa1/ras1 20 v ccqh 45 v ccp 70 aa0/ras0 21 hds /hds, hwr /hwr, or pb12 46 pcap 71 bg 22 hrw, hrd /hrd, or pb11 47 gnd p 72 a0 23 hack /hack, hrrq /hrrq, or pb15 48 gnd p1 73 a1 24 horeq /horeq, htrq /htrq, or pb14 49 v ccqh 74 v cca 25 v ccs 50 aa3/ras3 75 gnd a
lqfp package description dsp56362 technical data, rev. 4 4-4 freescale semiconductor 76 a2 99 a17 122 d16 77 a3 100 d0 123 d17 78 a4 101 d1 124 d18 79 a5 102 d2 125 d19 80 v cca 103 v ccd 126 v ccql 81 gnd a 104 gnd d 127 gnd q 82 a6 105 d3 128 d20 83 a7 106 d4 129 v ccd 84 a8 107 d5 130 gnd d 85 a9 108 d6 131 d21 86 v cca 109 d7 132 d22 87 gnd a 110 d8 133 d23 88 a10 111 v ccd 134 modd/irqd 89 a11 112 gnd d 135 modc/irqc 90 gnd q 113 d9 136 modb/irqb 91 v ccql 114 d10 137 moda/irqa 92 a12 115 d11 138 trst 93 a13 116 d12 139 tdo 94 a14 117 d13 140 tdi 95 v ccqh 118 d14 141 tck 96 gnd a 119 v ccd 142 tms 97 a15 120 gnd d 143 mosi/ha0 98 a16 121 d15 144 miso/sda 1 signal names are based on configured func tionality. most pins supply a single signal. some pins provide a signal with dual functionality, such as the modx/irqx pins that select an operating mode after reset is deasserted, but act as interrupt lines during operation. some signals have configurable polar ity; these names are shown with and without overbars, such as has /has. some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. for example, pin 34 is data line h7 in nonmultiplexed bus mode, data/address line had7 in multiplexed bus mode, or gpio line pb7 when the gpio function is enabled for this pin. table 4-1 dsp56362 lqfp signal identification by pin number (continued) pin no. signal name 1 pin no. signal name 1 pin no. signal name 1
lqfp package description dsp56362 technical data, rev. 4 freescale semiconductor 4-5 table 4-2 dsp56362 lqfp signal identification by name signal name pin no. signal na me pin no. signal name pin no. not connected 60 d13 117 gnd p1 48 a0 72 d14 118 gnd q 19 a1 73 d15 121 gnd q 54 a10 88 d16 122 gnd q 90 a11 89 d17 123 gnd q 127 a12 92 d18 124 gnd s 9 a13 93 d19 125 gnd s 26 a14 94 d2 102 h0 43 a15 97 d20 128 h1 42 a16 98 d21 131 h2 41 a17 99 d22 132 h3 40 a2 76 d23 133 h4 37 a3 77 d3 105 h5 36 a4 78 d4 106 h6 35 a5 79 d5 107 h7 34 a6 82 d6 108 ha0 33 a7 83 d7 109 ha0 143 a8 84 d8 110 ha1 32 a9 85 d9 113 ha10 30 aa0 70 de 53 ha2 2 aa1 69 extal 55 ha2 31 aa2 51 fsr 13 ha8 32 aa3 50 fst 12 ha9 31 aci 28 gnd a 75 hack /hack 23 ado 27 gnd a 81 had0 43 bb 64 gnd a 87 had1 42 bg 71 gnd a 96 had2 41
lqfp package description dsp56362 technical data, rev. 4 4-6 freescale semiconductor br 63 gnd c 58 had3 40 cas 52 gnd c 66 had4 37 clkout 59 gnd d 104 had5 36 d0 100 gnd d 112 had6 35 d1 101 gnd d 120 had7 34 d10 114 gnd d 130 has /has 33 d11 115 gnd h 39 hcs /hcs 30 d12 116 gnd p 47 hds /hds 21 horeq /horeq 24 pb9 32 sdo3 7 hrd /hrd 22 pc0 15 sdo4 10 hreq 3 pc1 13 sdo5 11 hrrq /hrrq 23 pc10 5 ss 2 hrw 22 pc11 4 ta 62 hckr 17 pc2 17 tck 141 hckt 16 pc3 14 tdi 140 htrq /htrq 24 pc4 12 tdo 139 hwr /hwr 21 pc5 16 tio0 29 irqa 137 pc6 11 tms 142 irqb 136 pc7 10 trst 138 irqc 135 pc8 7 v cca 74 irqd 134 pc9 6 v cca 80 miso 144 pcap 46 v cca 86 moda 137 pd0 28 v ccc 57 modb 136 pd1 27 v ccc 65 modc 135 pinit 61 v ccd 103 modd 134 ras0 70 v ccd 111 mosi 143 ras1 69 v ccd 119 table 4-2 dsp56362 lqfp signal identification by name (continued) signal name pin no. signal na me pin no. signal name pin no.
lqfp package description dsp56362 technical data, rev. 4 freescale semiconductor 4-7 nmi 61 ras2 52 v ccd 129 pb0 43 ras3 51 v cch 38 pb1 42 rd 68 v ccp 45 pb10 31 reset 44 v ccqh 20 pb11 22 sck 1 v ccqh 49 pb12 21 sckr 15 v ccqh 95 pb13 30 sckt 14 v ccql 18 pb14 24 scl 1 v ccql 56 pb15 23 sda 144 v ccql 91 pb2 41 sdi0 11 v ccql 126 pb3 40 sdi1 10 v ccs 8 pb4 37 sdi2 7 v ccs 25 pb5 36 sdi3 6 wr 67 pb6 35 sdo0 4 pb7 34 sdo1 5 pb8 33 sdo2 6 table 4-2 dsp56362 lqfp signal identification by name (continued) signal name pin no. signal na me pin no. signal name pin no.
lqfp package mechanical drawing dsp56362 technical data, rev. 4 4-8 freescale semiconductor 4.3 lqfp package mechanical drawing figure 4-2 dsp56362 144-pin lqfp package
dsp56362 technical data, rev. 4 freescale semiconductor 5-1 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package w historically, thermal resistance has been expressed as the sum of a ju nction-to-case thermal resistance and a case-to-ambient thermal resistance. where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the ther mal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the pr inted circuit board (pcb), or otherwise change the thermal dissi pation capability of the area surr ounding the device on a pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient envi ronment. for ceramic packages, in situations where the heat flow is split between a path to the case an d an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capabili ty of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactori ly answer whether the thermal performance is adequate, a sy stem level model may be appropriate. a complicating factor is the existence of three comm on ways for determining th e junction-to-case thermal resistance in plastic packages. t j t a p d r ja () + = r ja r jc r ca + =
electrical design considerations dsp56362 technical data, rev. 4 5-2 freescale semiconductor ? to minimize temperature variation across the surface, the thermal resi stance is measured from the junction to the outside surface of the package (case) closest to th e chip mounting area when that surface has a proper heat sink. ? to define a value approximately equal to a j unction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a thermoc ouple, the thermal resistance is computed using the va lue obtained by the equation (t j ? t t )/p d . as noted above, the junction-to-case th ermal resistances quoted in this da ta sheet are determined using the first definition. from a practical standpoint, that va lue is also suitable for determining the junction temperature from a case thermocoupl e reading in forced convection e nvironments. in natural convection, using the junction-to-case thermal resistance to es timate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slight ly hotter than actual temperature. hence, the new thermal metr ic, thermal characteri zation parameter or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temp erature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by in adequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. th e recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 electrical design considerations caution this device contains circuitry protecti ng against damage due to high static voltage or electrical fields. however, normal preca utions should be taken to avoid exceeding maximum voltage ra tings. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 k ohm. use the following list of recommendati ons to assure correct dsp operation: ? provide a low-impedanc e path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. ? use at least six 0.01?0.1 f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v cc and gnd pins are less than 1.2 cm (0.5 inch) per capacitor lead. ? use at least a four-layer pc b with two inner layers for v cc and gnd. ? because the dsp output signals have fast rise and fall times, pcb trace lengths shoul d be minimal. this recommendation particularly applies to th e address and data buses as well as the irqa , irqb , irqc , irqd , ta , and bg pins. maximum pcb trace lengths on the order of 15 cm (6 inches) are recommended.
power consumption considerations dsp56362 technical data, rev. 4 freescale semiconductor 5-3 ? consider all device loads as we ll as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher ca pacitive loads that could create higher transient currents in the v cc and gnd circuits. ? all inputs must be terminated (i .e., not allowed to float) using cm os levels, except for the pins with internal pull-up resistors (trst , tms, de, tck, and tdi ). ? take special care to mini mize noise levels on the v ccp , gnd p , and gnd p1 pins. ? if multiple dsp56362 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. ? reset must be asserted when the chip is pow ered up. a stable extal signal should be supplied before deassertion of reset. ? at power-up, ensure that the voltage difference between the 5 v tolerant pins and the chip v cc never exceeds 3.95 v. 5.3 power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors which affect current consumption are descri bed in this section. most of the current consumed by cm os devices is alternating current (ac), which is charging a nd discharging the capacitances of the pins and internal nodes. current consumption is descri bed by the following formula: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle the maximum internal current (i cci max) value reflects the typical possi ble switching of the internal buses on best-case operation conditions, which is not necessarily a real applic ation case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typi cal operating conditions. for applications that require very lo w current consumption, do the following: ? set the ebd bit when not accessing external memory. ? minimize external memory accesses and use internal memory accesses. ? minimize the number of pins that are switching. ? minimize the capacitive load on the pins. ? connect the unused inputs to pull-up or pull-down resistors. example 1. current consumption for a port a address pin loaded with 50 pf capacitance, operating at 3.3 v, and with a 100 mhz clock, toggling at its maximum possible rate (50 mhz), the current consumption is icv f = i5010 12 ? 3.3 50 10 6 8.25ma ==
pll performance issues dsp56362 technical data, rev. 4 5-4 freescale semiconductor ? disable unused peripherals. ? disable unused pin activity (e.g., clkout, xtal). one way to evaluate power consum ption is to use a current per mips measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the dsp). a benchmark power consumption te st algorithm is listed in appendix a . use the test algorithm, specific test current measurements, and the following e quation to derive the current per mips value. where : i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any speci fied operating frequency) f1 = low frequency (any specified ope rating frequency lower than f2) note f1 should be significantly less than f2. for example, f2 could be 66 mhz and f1 could be 33 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current rating can be determined for an application. 5.4 pll performance issues the following explanations should be considered as general observations on expected pll behavior. there is no testing that verifies these exact numbe rs. these observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 5.4.1 phase skew performance the phase skew of the pll is defined as the time difference between the fa lling edges of extal and clkout for a given capacitive load on clkout, over the entire process, te mperature, and voltage ranges. as defined in figure 3-1 , for input frequencies great er than 15 mhz and the mf 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; ot herwise, this skew is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this skew is between ? 1.4 ns and +3.2 ns. 5.4.2 phase jitter performance the phase jitter of the pll is defined as the variat ions in the skew between the falling edges of extal and clkout for a given device in sp ecific temperature, voltage, input frequency, mf, and capacitive load on clkout. these variations are a result of the p ll locking mechanism. for input frequencies greater than 15 mhz and mf 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. however, for mf < 10 and input frequencies greater th an 10 mhz, this jitter is less than 2 ns. 1mips 1mhz i ( typf2 i typf1 ) f2 f1 ? () ? ==
host port considerations dsp56362 technical data, rev. 4 freescale semiconductor 5-5 5.4.3 frequency jitter performance the frequency jitter of the pll is defined as the variation of the frequency of clkout. for small mf (mf < 10) this jitter is smaller than 0.5%. for mid-range mf (10 < mf < 500) this jitt er is between 0.5% and approximately 2%. for large mf (m f > 500), the frequency jitter is 2?3%. 5.4.4 input (extal) jitter requirements the allowed jitter on the fre quency of extal is 0.5%. if the rate of change of the frequency of extal is slow (i.e., it does not jump be tween the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a l ong time), then the allowed jitter can be 2%. the phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5.5 host port considerations careful synchronization is require d when reading multi-bit regist ers that are written by another asynchronous system. this synchron ization is a common problem wh en two asynchronous systems are connected, as they are in the host interface. the fo llowing paragraphs present considerations for proper operation. 5.5.1 host programming considerations ? unsynchronized reading of receive byte registers ?when reading the receive byte registers, receive register high (rxh), receive register middle (rxm), or receive register low (rxl), the host interface programmer shoul d use interrupts or poll the receive register da ta full (rxdf) flag that indicates whether data is ava ilable. this ensures that the data in the receive byte registers will be valid. ? overwriting transmit byte registers ?the host interface programmer should not write to the transmit byte registers, transmit register high (txh), transmit register middle (txm), or transmit register low (txl), unless the transmit register da ta empty (txde) bit is set, indicating that the transmit byte registers are empty. this ensures that the transmit byt e registers will transfer valid data to the host receive (hrx) register. ? synchronization of status bits from dsp to host ?hc, horeq , dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsp and read by the host processor (refer to the user?s manual for desc riptions of these status bits). th e host can read these status bits very quickly without regard to the clock rate used by the dsp, but the state of the bit could be changing during the read operation. th is is not generally a system probl em, because the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts hen for more than timing number 31, with a minimum cycle time of timing number 31 + 32, th en these status bits are guaranteed to be stable. exercise care when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a smal l probability that the hos t could read the bits during the transition and receive 01 or 10 instead of 11. if the combinati on of hf3 and hf2 has
host port considerations dsp56362 technical data, rev. 4 5-6 freescale semiconductor significance, the host could read the wrong comb ination. therefore, read the bits twice and check for consensus. ? overwriting the host vector ?the host interface programmer should change the host vector (hv) register only when the host command (hc) bit is clear. this ensures that the dsp interrupt control logic will receive a stable vector. ? cancelling a pending host command exception ?the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the ex ception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host command exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time that the hc bit is cleared. ? variance in the host interface timing ?the host interface (hdi) may vary (e.g. due to the pll lock time at reset). therefore, a host which attempts to load (boot strap) the dsp sh ould first make sure that the part has completed its hi port pr ogramming (e.g., by setting the init bit in icr then polling it and waiting it to be cl eared, then reading the isr or by writing the treq/rreq together with the init and then polling init, isr, and the horeq pin). 5.5.2 dsp programming considerations ? synchronization of status bits from host to dsp ?dma, hf1, hf0, hcp, htde, and hrdf status bits are set or cleared by the host processor side of the inte rface. these bits are individually synchronized to the dsp clock. (refer to the user?s manual for descriptions of these status bits.) ? reading hf0 and hf1 as an encoded pair ?care must be exercised when reading status bits hf0 and hf1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). a very small probability exists that the dsp will read the st atus bits synchronized during transition. therefore, hf0 and hf1 shoul d be read twice and checked for consensus.
dsp56362 technical data, rev. 4 freescale semiconductor 6-1 6 ordering information consult a freescale semiconductor, in c. sales office or authorized distributor to determine product availability and to place an order. for information on ordering this and all dsp audi o products, review the sg1004 selector guide at http://www.freescale.com .
dsp56362 technical data, rev. 4 6-2 freescale semiconductor notes
dsp56362 technical data, rev. 4 freescale semiconductor a-1 appendix a power consumption benchmark the following benchmark program perm its evaluation of dsp power usage in a test situation. it enables the pll, disables the external cloc k, and uses repeated mu ltiply-accumulate instru ctions with a set of synthetic dsp application data to em ulate intensive sustained dsp operation. ;********************************************************************;********* *********************************************************** ;* ;* checks typical power consumption ;******************************************************************** page 200,55,0,0,0 nolist i_vec equ $000000 ; interrupt vectors for program debug only start equ $8000 ; main (external) program starting address int_prog equ $100 ; internal program memory starting address int_xdat equ $0 ; internal x-data memory starting address int_ydat equ $0 ; internal y-data memory starting address include "ioequ.asm" include "intequ.asm" list org p:start ; movep #$0123ff,x:m_bcr; bcr: area 3 : 1 w.s (sram) ; default: 1 w.s (sram) ; movep #$0d0000,x:m_pctl ; xtal disable ; pll enable ; clkout disable ; ; load the program ; move #int_prog,r0 move #prog_start,r1 do #(prog_end-prog_start),pload_loop move p:(r1)+,x0 move x0,p:(r0)+ nop pload_loop ; ; load the x-data ; move #int_xdat,r0 move #xdat_start,r1
dsp56362 technical data, rev. 4 a-2 freescale semiconductor do #(xdat_end-xdat_start),xload_loop move p:(r1)+,x0 move x0,x:(r0)+ xload_loop ; ; load the y-data ; move #int_ydat,r0 move #ydat_start,r1 do #(ydat_end-ydat_start),yload_loop move p:(r1)+,x0 move x0,y:(r0)+ yload_loop ; jmp int_prog prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd ; sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop prog_end nop nop xdat_start ; org x:0 dc $262eb9 dc $86f2fe dc $e56a5f dc $616cac
dsp56362 technical data, rev. 4 freescale semiconductor a-3 dc $8ffd75 dc $9210a dc $a06d7b dc $cea798 dc $8dfbf1 dc $a063d6 dc $6c6657 dc $c2a544 dc $a3662d dc $a4e762 dc $84f0f3 dc $e6f1b0 dc $b3829 dc $8bf7ae dc $63a94f dc $ef78dc dc $242de5 dc $a3e0ba dc $ebab6b dc $8726c8 dc $ca361 dc $2f6e86 dc $a57347 dc $4be774 dc $8f349d dc $a1ed12 dc $4bfce3 dc $ea26e0 dc $cd7d99 dc $4ba85e dc $27a43f dc $a8b10c dc $d3a55 dc $25ec6a dc $2a255b dc $a5f1f8 dc $2426d1 dc $ae6536 dc $cbbc37 dc $6235a4 dc $37f0d dc $63bec2 dc $a5e4d3 dc $8ce810 dc $3ff09 dc $60e50e dc $cffb2f dc $40753c dc $8262c5 dc $ca641a dc $eb3b4b dc $2da928 dc $ab6641 dc $28a7e6 dc $4e2127
dsp56362 technical data, rev. 4 a-4 freescale semiconductor dc $482fd4 dc $7257d dc $e53c72 dc $1a8c3 dc $e27540 xdat_end ydat_start ; org y:0 dc $5b6da dc $c3f70b dc $6a39e8 dc $81e801 dc $c666a6 dc $46f8e7 dc $aaec94 dc $24233d dc $802732 dc $2e3c83 dc $a43e00 dc $c2b639 dc $85a47e dc $abfddf dc $f3a2c dc $2d7cf5 dc $e16a8a dc $ecb8fb dc $4bed18 dc $43f371 dc $83a556 dc $e1e9d7 dc $aca2c4 dc $8135ad dc $2ce0e2 dc $8f2c73 dc $432730 dc $a87fa9 dc $4a292e dc $a63ccf dc $6ba65c dc $e06d65 dc $1aa3a dc $a1b6eb dc $48ac48 dc $ef7ae1 dc $6e3006 dc $62f6c7 dc $6064f4 dc $87e41d dc $cb2692 dc $2c3863 dc $c6bc60 dc $43a519 dc $6139de dc $adf7bf
dsp56362 technical data, rev. 4 freescale semiconductor a-5 dc $4b3e8c dc $6079d5 dc $e0f5ea dc $8230db dc $a3b778 dc $2bfe51 dc $e0a6b6 dc $68ffb7 dc $28f324 dc $8f2e8d dc $667842 dc $83e053 dc $a1fd90 dc $6b2689 dc $85b68e dc $622eaf dc $6162bc dc $e4a245 ydat_end
dsp56362 technical data, rev. 4 a-6 freescale semiconductor notes
dsp56362 technical data, rev. 4 freescale semiconductor b-1 appendix b ibis model [ibis ver] 2.1 [file name] 56362.ibs [file rev] 0.0 [date] 29/6/2000 [component] 56362 [manufacturer] freescale [package] |variable typ min max r_pkg 45m 22m 75m l_pkg 2.5nh 1.1nh 4.3nh c_pkg 1.3pf 1.2pf 1.4pf [pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io 30 hp13 ip5b_io 31 hp10 ip5b_io 32 hp9 ip5b_io
dsp56362 technical data, rev. 4 b-2 freescale semiconductor 33 hp8 ip5b_io 34 hp7 ip5b_io 35 hp6 ip5b_io 36 hp5 ip5b_io 37 hp4 ip5b_io 38 svcc power 39 sgnd gnd 40 hp3 ip5b_io 41 hp2 ip5b_io 42 hp1 ip5b_io 43 hp0 ip5b_io 44 ires_ ip5b_i 45 pvcc power 46 pcap power 47 pgnd gnd 48 pgnd1 gnd 49 qvcch power 50 aa3 icbc_o 51 aa2 icbc_o 52 cas_ icbc_o 53 de_ ipbw_io 54 qgnd gnd 55 cxtldis_ iexlh_i 56 qvccl power 57 cvcc power 58 cgnd gnd 59 clkout icba_o 61 nmi_ ipbw_i 62 ta_ icbc_o 63 br_ icbc_o 64 bb_ icbc_o 65 cvcc power 66 cgnd gnd 67 wr_ icbc_o 68 rd_ icbc_o 69 aa1 icbc_o 70 aa0 icbc_o 71 bg_ icbc_o 72 eab0 icba_o 73 eab1 icba_o 74 avcc power 75 agnd gnd 76 eab2 icba_o 77 eab3 icba_o 78 eab4 icba_o 79 eab5 icba_o 80 avcc power 81 agnd gnd 82 eab6 icba_o 83 eab7 icba_o 84 eab8 icba_o 85 eab9 icba_o 86 avcc power 87 agnd gnd 88 eab10 icba_o
dsp56362 technical data, rev. 4 freescale semiconductor b-3 89 eab11 icba_o 90 qgnd gnd 91 qvcc power 92 eab12 icba_o 93 eab13 icba_o 94 eab14 icba_o 95 qvcch power 96 agnd gnd 97 eab15 icba_o 98 eab16 icba_o 99 eab17 icba_o 100 edb0 icba_io 101 edb1 icba_io 102 edb2 icba_io 103 dvcc power 104 dgnd gnd 105 edb3 icba_io 106 edb4 icba_io 107 edb5 icba_io 108 edb6 icba_io 109 edb7 icba_io 110 edb8 icba_io 111 dvcc power 112 dgnd gnd 113 edb9 icba_io 114 edb10 icba_io 115 edb11 icba_io 116 edb12 icba_io 117 edb13 icba_io 118 edb14 icba_io 119 dvcc power 120 dgnd gnd 121 edb15 icba_io 122 edb16 icba_io 123 edb17 icba_io 124 edb18 icba_io 125 edb19 icba_io 126 qvccl power 127 qgnd gnd 128 edb20 icba_io 129 dvcc power 130 dgnd gnd 131 edb21 icba_io 132 edb22 icba_io 133 edb23 icba_io 134 irqd_ ip5b_i 135 irqc_ ip5b_i 136 irqb_ ip5b_i 137 irqa_ ip5b_i 138 trst_ ip5b_i 139 tdo ip5b_o 140 tdi ip5b_i 141 tck ip5b_i 142 tms ip5b_i 143 mosi ip5b_io
dsp56362 technical data, rev. 4 b-4 freescale semiconductor 144 sda ip5b_io | [model] ip5b_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | | [model] ip5b_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02
dsp56362 technical data, rev. 4 freescale semiconductor b-5 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04 -1.70e+00 2.812e-04 2.520e-04 3.808e-04
dsp56362 technical data, rev. 4 b-6 freescale semiconductor -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03 3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02 5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02 7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02 9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02 1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02 1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02 1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02 1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02 1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02 2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02 2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02 2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02 2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02 2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02 3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02 3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02 3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02 3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02 3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02 4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02 4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02 4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02 4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02
dsp56362 technical data, rev. 4 freescale semiconductor b-7 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dv/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [model] ip5b_o model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02
dsp56362 technical data, rev. 4 b-8 freescale semiconductor 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04 -1.70e+00 2.812e-04 2.520e-04 3.808e-04 -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03 3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02 5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02 7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02 9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02 1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02 1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02
dsp56362 technical data, rev. 4 freescale semiconductor b-9 1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02 1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02 1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02 2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02 2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02 2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02 2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02 2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02 3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02 3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02 3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02 3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02 3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02 4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02 4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02 4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02 4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | |
dsp56362 technical data, rev. 4 b-10 freescale semiconductor dv/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dv/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [model] icba_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01
dsp56362 technical data, rev. 4 freescale semiconductor b-11 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02 1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02 1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01 1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01 1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01 2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01 2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01 2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01 2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01 2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01 3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01 3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01 3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01 3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01 3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01
dsp56362 technical data, rev. 4 b-12 freescale semiconductor 4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01 4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01 4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01 4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00 4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05
dsp56362 technical data, rev. 4 freescale semiconductor b-13 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dv/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [model] icba_o model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01
dsp56362 technical data, rev. 4 b-14 freescale semiconductor 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02 1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02 1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01 1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01 1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01 2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01 2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01 2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01
dsp56362 technical data, rev. 4 freescale semiconductor b-15 2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01 2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01 3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01 3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01 3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01 3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01 3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01 4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01 4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01 4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01 4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00 4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01
dsp56362 technical data, rev. 4 b-16 freescale semiconductor -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dv/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [model] icbc_o model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02
dsp56362 technical data, rev. 4 freescale semiconductor b-17 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01 5.100e+00 7.505e+01 8.210e+01 4.384e+01 5.300e+00 1.007e+02 1.000e+02 6.224e+01 5.500e+00 1.264e+02 1.179e+02 8.794e+01 5.700e+00 1.522e+02 1.359e+02 1.136e+02 5.900e+00 1.779e+02 1.538e+02 1.394e+02 6.100e+00 2.036e+02 1.717e+02 1.651e+02 6.300e+00 2.293e+02 1.896e+02 1.908e+02 6.500e+00 2.550e+02 2.075e+02 2.165e+02 6.600e+00 2.678e+02 2.165e+02 2.293e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.677e+02 1.896e+02 2.677e+02 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.302e+00 1.433e+01 9.303e+00 -9.00e-01 3.838e-02 2.477e+00 4.183e-02 -7.00e-01 8.115e-03 1.789e-02 1.045e-02 -5.00e-01 5.634e-03 3.503e-03 7.064e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02
dsp56362 technical data, rev. 4 b-18 freescale semiconductor 1.300e+00 -1.03e-02 -4.75e-02 -1.41e-02 1.500e+00 -9.03e-02 -5.02e-02 -1.23e-01 1.700e+00 -9.49e-02 -5.21e-02 -1.31e-01 1.900e+00 -9.84e-02 -5.34e-02 -1.38e-01 2.100e+00 -1.01e-01 -5.45e-02 -1.43e-01 2.300e+00 -1.03e-01 -5.54e-02 -1.47e-01 2.500e+00 -1.05e-01 -5.62e-02 -1.50e-01 2.700e+00 -1.06e-01 -5.68e-02 -1.52e-01 2.900e+00 -1.07e-01 -5.74e-02 -1.54e-01 3.100e+00 -1.08e-01 -5.79e-02 -1.56e-01 3.300e+00 -1.09e-01 -5.84e-02 -1.57e-01 3.500e+00 -1.10e-01 -5.89e-02 -1.59e-01 3.700e+00 -1.11e-01 -6.49e-02 -1.60e-01 3.900e+00 -1.11e-01 -1.23e+00 -1.61e-01 4.100e+00 -1.14e-01 -2.16e+01 -1.62e-01 4.300e+00 -4.76e-01 -4.52e+01 -1.64e-01 4.500e+00 -2.73e+01 -6.89e+01 -1.73e-01 4.700e+00 -6.14e+01 -9.25e+01 -7.82e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.19e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -1.03e-02 -1.17e+00 -9.27e-03 -7.00e-01 -3.74e-04 -5.73e-03 -1.14e-03 -5.00e-01 -1.72e-06 -5.06e-05 -1.28e-05 -3.00e-01 -1.67e-09 -4.65e-07 -1.10e-08 -1.00e-01 -2.03e-11 -4.80e-09 -2.71e-11 0.000e+00 -1.69e-11 -1.61e-09 -1.89e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.677e+02 1.896e+02 2.677e+02
dsp56362 technical data, rev. 4 freescale semiconductor b-19 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.300e+00 1.433e+01 9.301e+00 -9.00e-01 2.962e-02 2.475e+00 3.075e-02 -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 -1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dv/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | | [model] ipbw_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04
dsp56362 technical data, rev. 4 b-20 freescale semiconductor -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | | [model] ipbw_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02
dsp56362 technical data, rev. 4 freescale semiconductor b-21 -3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02 -1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02 1.900e+00 4.347e-02 2.136e-02 5.518e-02 2.100e+00 4.413e-02 2.162e-02 5.728e-02 2.300e+00 4.445e-02 2.176e-02 5.843e-02 2.500e+00 4.465e-02 2.186e-02 5.899e-02 2.700e+00 4.479e-02 2.194e-02 5.931e-02 2.900e+00 4.492e-02 2.200e-02 5.953e-02 3.100e+00 4.502e-02 2.206e-02 5.971e-02 3.300e+00 4.511e-02 2.211e-02 5.986e-02 3.500e+00 4.519e-02 2.219e-02 5.999e-02 3.700e+00 4.526e-02 3.324e-02 6.010e-02 3.900e+00 4.536e-02 2.452e+00 6.021e-02 4.100e+00 4.614e-02 1.423e+01 6.032e-02 4.300e+00 1.344e+00 2.615e+01 6.065e-02 4.500e+00 1.783e+01 3.808e+01 8.548e-02 4.700e+00 3.495e+01 5.001e+01 9.298e+00 4.900e+00 5.208e+01 6.371e+01 2.640e+01 5.100e+00 7.463e+01 8.154e+01 4.352e+01 5.300e+00 1.002e+02 9.937e+01 6.184e+01 5.500e+00 1.259e+02 1.172e+02 8.745e+01 5.700e+00 1.515e+02 1.350e+02 1.131e+02 5.900e+00 1.771e+02 1.529e+02 1.387e+02 6.100e+00 2.027e+02 1.707e+02 1.643e+02 6.300e+00 2.283e+02 1.885e+02 1.899e+02 6.500e+00 2.539e+02 2.064e+02 2.155e+02 6.600e+00 2.667e+02 2.153e+02 2.283e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.635e+01 2.613e+01 2.635e+01 -1.10e+00 9.243e+00 1.421e+01 9.245e+00 -9.00e-01 5.536e-02 2.435e+00 6.260e-02 -7.00e-01 2.847e-02 2.689e-02 3.437e-02 -5.00e-01 2.025e-02 1.265e-02 2.451e-02
dsp56362 technical data, rev. 4 b-22 freescale semiconductor -3.00e-01 1.208e-02 7.503e-03 1.467e-02 -1.00e-01 3.994e-03 2.474e-03 4.868e-03 1.000e-01 -3.88e-03 -2.38e-03 -4.76e-03 3.000e-01 -1.11e-02 -6.76e-03 -1.37e-02 5.000e-01 -1.76e-02 -1.06e-02 -2.20e-02 7.000e-01 -2.35e-02 -1.40e-02 -2.95e-02 9.000e-01 -2.86e-02 -1.69e-02 -3.63e-02 1.100e+00 -3.30e-02 -1.93e-02 -4.23e-02 1.300e+00 -3.65e-02 -2.10e-02 -4.75e-02 1.500e+00 -3.92e-02 -2.22e-02 -5.17e-02 1.700e+00 -4.12e-02 -2.29e-02 -5.51e-02 1.900e+00 -4.26e-02 -2.35e-02 -5.77e-02 2.100e+00 -4.36e-02 -2.38e-02 -5.97e-02 2.300e+00 -4.43e-02 -2.42e-02 -6.11e-02 2.500e+00 -4.49e-02 -2.44e-02 -6.22e-02 2.700e+00 -4.54e-02 -2.47e-02 -6.31e-02 2.900e+00 -4.58e-02 -2.49e-02 -6.38e-02 3.100e+00 -4.61e-02 -2.50e-02 -6.44e-02 3.300e+00 -4.65e-02 -2.52e-02 -6.49e-02 3.500e+00 -4.68e-02 -2.54e-02 -6.54e-02 3.700e+00 -4.70e-02 -2.99e-02 -6.58e-02 3.900e+00 -4.73e-02 -1.19e+00 -6.62e-02 4.100e+00 -4.81e-02 -2.15e+01 -6.66e-02 4.300e+00 -4.00e-01 -4.51e+01 -6.72e-02 4.500e+00 -2.72e+01 -6.87e+01 -7.21e-02 4.700e+00 -6.12e+01 -9.24e+01 -7.70e+00 4.900e+00 -9.52e+01 -1.17e+02 -4.17e+01 5.100e+00 -1.37e+02 -1.52e+02 -7.57e+01 5.300e+00 -1.88e+02 -1.88e+02 -1.10e+02 5.500e+00 -2.39e+02 -2.23e+02 -1.60e+02 5.700e+00 -2.90e+02 -2.58e+02 -2.11e+02 5.900e+00 -3.41e+02 -2.94e+02 -2.62e+02 6.100e+00 -3.92e+02 -3.29e+02 -3.13e+02 6.300e+00 -4.43e+02 -3.65e+02 -3.64e+02 6.500e+00 -4.94e+02 -4.00e+02 -4.15e+02 6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06
dsp56362 technical data, rev. 4 freescale semiconductor b-23 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dv/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | | [model] iexlh_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02
dsp56362 technical data, rev. 4 b-24 freescale semiconductor -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 -1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02 -1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01 -1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01 -1.10e+00 -1.13e+01 -2.26e+01 -8.78e+00 -9.00e-01 -7.94e-03 -1.87e+00 -3.77e-03 -7.00e-01 -1.62e-06 -5.11e-03 -7.69e-07 -5.00e-01 -3.45e-10 -1.40e-05 -1.72e-10 -3.00e-01 -1.29e-11 -3.90e-08 -1.38e-11 -1.00e-01 -1.10e-11 -8.67e-10 -1.19e-11 0.000e+00 -1.01e-11 -7.13e-10 -1.10e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.653e+02 1.870e+02 2.653e+02 -3.10e+00 2.398e+02 1.693e+02 2.398e+02 -2.90e+00 2.143e+02 1.516e+02 2.143e+02 -2.70e+00 1.888e+02 1.339e+02 1.888e+02 -2.50e+00 1.633e+02 1.162e+02 1.633e+02 -2.30e+00 1.378e+02 9.847e+01 1.378e+02 -2.10e+00 1.123e+02 8.076e+01 1.123e+02 -1.90e+00 8.682e+01 6.305e+01 8.682e+01 -1.70e+00 6.133e+01 4.947e+01 6.133e+01 -1.50e+00 4.313e+01 3.766e+01 4.313e+01 -1.30e+00 2.614e+01 2.585e+01 2.614e+01 -1.10e+00 9.145e+00 1.404e+01 9.145e+00 -9.00e-01 1.797e-02 2.364e+00 1.797e-02 -7.00e-01 3.667e-06 7.589e-03 3.667e-06 -5.00e-01 7.730e-10 2.072e-05 7.748e-10 -3.00e-01 2.293e-11 5.767e-08 2.476e-11 -1.00e-01 2.096e-11 1.163e-09 2.278e-11 0.000e+00 2.004e-11 9.618e-10 2.186e-11 | [end]
dsp56362 technical data, rev. 4 freescale semiconductor index-1 index a ac electrical characteristics 3 address trace mode 3, 38, 41 applications 5 arbitration bus timings 41 b bootstrap rom 3 boundary scan (jtag port) timing diagram 72 bus address 2 data 2 multiplexed 2 non-multiplexed 2 bus acquisition timings 42 bus release timings 43, 44 c clock external 4 operation 5 clocks internal 4 d data memory expansion 4 dax 4, 2, 16 dc electrical ch aracteristics 2 debug support 3 design considerations electrical 3 pll 4, 5 power consumption 3 thermal 1 digital audio transmitter 4, 16 dram out of page read access 36 wait states selection guide 28 write access 37 out of page and refresh timings 11 wait states 32 15 wait states 33 4 wait states 28 8 wait states 30 page mode read accesses 27 wait states selection guide 19 write accesses 26 page mode timings 1 wait state 19 2 wait states 21 3 wait states 22 4 wait states 24 refresh access 38 dram controller 4 dsp programming 6 e electrical design considerations 3 enhanced serial audio interface 4 esai 4, 2 essi receiver timing 66, 67 timings 62 transmitter timing 65 extal jitter 5 external bus control 6, 7 external bus synchronous timings (sram access)
dsp56362 technical data, rev. 4 index-2 freescale semiconductor 38 external clock operation 4 external interrupt timing (negative edge-triggered) 11 external level-sensitive fast interrupt timing 11 external memory access (dma source) timing 13 external memory expansion port 14 f functional groups 2 functional signal groups 1 g general purpose input/output 4 gpio 4, 2, 19 gpio timing 69 ground 4 pll 4 h hdi08 4, 2, 10, 12, 13 dsp programming 6 dsp synchronization 6 host synchronization 5 hdi08 timing 46 host interface 4, 2, 10, 12, 13 host interface timing 46 host port configuration 9 host port considerations 5 host programming 5 host request double 2 single 2 i instruction cache 3 internal clocks 4 interrupt and mode control 8 interrupt control 8 interrupt timing 7 external level-sensitive fast 11 external negative edge-triggered 11 synchronous from wait state 12 j jitter 5 jtag 20 jtag port 3 reset timing diagram 73 timing 70, 72 m maximum ratings 1 memory expansion port 3 mode control 8 mode select timing 7 multiplexed bus 2 multiplexed bus timings read 50 write 51 n non-multiplexed bus 2 non-multiplexed bus timings read 48 write 49
dsp56362 technical data, rev. 4 freescale semiconductor index-3 o off-chip memory 3 once module timing 73 once module 3, 20 debug request 73 on-chip dram controller 4 on-chip emulation module 3 on-chip memory 3 operating mode select timing 12 p package 144-pin tqfp 1 tqfp description 1, 3 phase lock loop 6 pll 6 characteristics 6 performance issues 4 pll design considerations 4, 5 pll performance issues 5 port a 2 port b 2, 10, 11, 12, 13 port c 2, 16 port d 2, 16 power consumption desi gn considerations 3 power management 5 program memory expansion 4 program ram 3 r recovery from stop state using irqa 12, 13 reset 9 reset timing 7, 10 synchronous 10 rom, bootstrap 3 s serial host interface 4, 14 shi 4, 2, 14 signal groupings 1 signals 1 functional grouping 2 sram 40 access 38 read access 17 read and write accesses 14 support 4 write access 17, 18 stop mode 5 stop state recovery from 12, 13 stop timing 7 supply voltage 1 switch mode 3 synchronization 5 synchronous bus timings sram 2 wait states 41 sram 1 wait state (bcr controlled) 40 synchronous interrupt from wait state timing 12 synchronous reset timing 10 t tap 3 target applications 5 test access port 3 test access port timing diagram 72 test clock (tclk) input timing diagram 71 thermal characteristics 2 thermal design c onsiderations 1 timer 4, 2, 19 event input restrictions 68 interrupt generation 68 timing 68 timing digital audio tran smitter (dax) 67
dsp56362 technical data, rev. 4 index-4 freescale semiconductor general purpose i/o (gpio) timing 62 once? (on chip emulator) timing 62 serial host interface (shi) spi protocol tim- ing 52 serial host interface (shi) timing 52 timing interrupt 7 mode select 7 reset 7 stop 7 tqfp 1 pin list by number 3 pin-out drawing (top) 1 w wait mode 5 x x data ram 3 y y data ram 3
dsp56362 technical data, rev. 4 freescale semiconductor index-5
document number: dsp56362 rev. 4 08/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved.

▲Up To Search▲

Price & Availability of DSP56300FM

	To Download DSP56300FM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .